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23S08E-2DCI8 PDF预览

23S08E-2DCI8

更新时间: 2024-02-21 05:16:36
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
11页 78K
描述
PLL Based Clock Driver, 23S Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, SOIC-16

23S08E-2DCI8 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.73
Is Samacsys:N系列:23S
输入调节:STANDARDJESD-30 代码:R-PDSO-G16
JESD-609代码:e0逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.008 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:16实输出次数:8
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.4 ns
子类别:Clock Drivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20最小 fmax:200 MHz
Base Number Matches:1

23S08E-2DCI8 数据手册

 浏览型号23S08E-2DCI8的Datasheet PDF文件第2页浏览型号23S08E-2DCI8的Datasheet PDF文件第3页浏览型号23S08E-2DCI8的Datasheet PDF文件第4页浏览型号23S08E-2DCI8的Datasheet PDF文件第5页浏览型号23S08E-2DCI8的Datasheet PDF文件第6页浏览型号23S08E-2DCI8的Datasheet PDF文件第7页 
3.3V ZERO DELAY CLOCK  
IDT23S08E  
MULTIPLIER, SPREAD  
SPECTRUM COMPATIBLE  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution for Applications ranging  
from 10MHz to 200MHz operating frequency  
• Distributes one clock input to two banks of four outputs  
• Separate output enable for each output bank  
• External feedback (FBK) pin is used to synchronize the outputs  
to the clock input  
TheIDT23S08Eisahigh-speedphase-lockloop(PLL)clockmultiplier. It  
isdesignedtoaddresshigh-speedclockdistributionandmultiplicationapplica-  
tions.Thezerodelayisachievedbyaligningthephasebetweentheincoming  
clockandtheoutputclock, operablewithintherangeof10to200MHz.  
TheIDT23S08Ehastwobanksoffouroutputseachthatarecontrolledvia  
twoselectaddresses.Byproperselectionofinputaddresses,bothbankscan  
beputintri-statemode.Intestmode,thePLListurnedoff,andtheinputclock  
directlydrivestheoutputsforsystemtestingpurposes. Intheabsenceofan  
inputclock,theIDT23S08Eenterspowerdown.Inthismode,thedevicewill  
• Output Skew <200 ps  
• Low jitter <200 ps cycle-to-cycle  
• 1x, 2x, 4x output options (see table):  
– IDT23S08E-1 1x  
– IDT23S08E-2 1x, 2x  
– IDT23S08E-3 2x, 4x  
drawlessthan1AforCommercialTemperaturerangeandlessthan25µA  
forIndustrialtemperaturerange,andtheoutputsaretri-stated.  
The IDT23S08E is available in six unique configurations for both pre-  
scaling and multiplication of the Input REF Clock. (See available options  
table.)  
ThePLLisclosedexternallytoprovidemoreflexibilitybyallowingtheuser  
tocontrolthedelaybetweentheinputclockandtheoutputs.  
The IDT23S08E is characterized for both Industrial and Commercial  
operation.  
– IDT23S08E-4 2x  
– IDT23S08E-1H, -2H, and -5H for High Drive  
• No external RC network required  
• Operates at 3.3V VDD  
• Spread spectrum compatible  
• Available in SOIC and TSSOP packages  
NOTE: EOL for non-green parts to occur on 5/13/10 per  
PDNU-09-01  
FUNCTIONALBLOCKDIAGRAM  
(-3, -4)  
16  
2
FBK  
REF  
2
CLKA1  
PLL  
1
2
(-5)  
3
CLKA2  
14  
CLKA3  
15  
CLKA4  
8
9
S2  
S1  
Control  
Logic  
2
(-2, -3)  
6
CLKB1  
CLKB2  
CLKB3  
CLKB4  
7
10  
11  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
AUGUST 2009  
1
c
2006 Integrated Device Technology, Inc.  
DSC 6499/7  

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