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23S08-3DC8 PDF预览

23S08-3DC8

更新时间: 2024-01-23 18:42:47
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
10页 74K
描述
PLL Based Clock Driver, 23S Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, SOIC-16

23S08-3DC8 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-16
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.73
Is Samacsys:N系列:23S
输入调节:STANDARDJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:10.3 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.008 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:16
实输出次数:8最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.4 ns
座面最大高度:2.65 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
最小 fmax:133.3 MHzBase Number Matches:1

23S08-3DC8 数据手册

 浏览型号23S08-3DC8的Datasheet PDF文件第2页浏览型号23S08-3DC8的Datasheet PDF文件第3页浏览型号23S08-3DC8的Datasheet PDF文件第4页浏览型号23S08-3DC8的Datasheet PDF文件第5页浏览型号23S08-3DC8的Datasheet PDF文件第6页浏览型号23S08-3DC8的Datasheet PDF文件第7页 
3.3V ZERO DELAY CLOCK  
IDT23S08  
MULTIPLIER, SPREAD  
SPECTRUM COMPATIBLE  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution for Applications ranging  
from 10MHz to 133MHz operating frequency  
• Distributes one clock input to two banks of four outputs  
• Separate output enable for each output bank  
• External feedback (FBK) pin is used to synchronize the outputs  
to the clock input  
TheIDT23S08isahigh-speedphase-lockloop(PLL)clockmultiplier.Itis  
designedtoaddresshigh-speedclockdistributionandmultiplicationapplica-  
tions.Thezerodelayisachievedbyaligningthephasebetweentheincoming  
clockandtheoutputclock, operablewithintherangeof10to133MHz.  
TheIDT23S08hastwobanksoffouroutputseachthatarecontrolledviatwo  
selectaddresses.Byproperselectionofinputaddresses,bothbankscanbe  
put in tri-state mode. In test mode, the PLL is turned off, and the input clock  
directlydrivestheoutputsforsystemtestingpurposes. Intheabsenceofan  
input clock, the IDT23S08 enters power down. In this mode, the device will  
• Output Skew <200 ps  
• Low jitter <200 ps cycle-to-cycle  
• 1x, 2x, 4x output options (see table):  
– IDT23S08-1 1x  
– IDT23S08-2 1x, 2x  
– IDT23S08-3 2x, 4x  
drawlessthan1AforCommercialTemperaturerangeandlessthan25µA  
forIndustrialtemperaturerange,andtheoutputsaretri-stated.  
The IDT23S08 is available in six unique configurations for both pre-  
scaling and multiplication of the Input REF Clock. (See available options  
table.)  
ThePLLisclosedexternallytoprovidemoreflexibilitybyallowingtheuser  
tocontrolthedelaybetweentheinputclockandtheoutputs.  
TheIDT23S08ischaracterizedforbothIndustrialandCommercialopera-  
tion.  
– IDT23S08-4 2x  
– IDT23S08-1H, -2H, and -5H for High Drive  
• No external RC network required  
• Operates at 3.3V VDD  
• Spread spectrum compatible  
• Available in SOIC and TSSOP packages  
NOTE: EOL for non-green parts to occur on 5/13/10 per  
PDNU-09-01  
FUNCTIONALBLOCKDIAGRAM  
(-3, -4)  
16  
2
FBK  
REF  
2
CLKA1  
PLL  
1
2
(-5)  
3
CLKA2  
14  
CLKA3  
15  
CLKA4  
8
9
S2  
S1  
Control  
Logic  
2
(-2, -3)  
6
CLKB1  
CLKB2  
CLKB3  
CLKB4  
7
10  
11  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
AUGUST 2009  
1
c
2003 Integrated Device Technology, Inc.  
DSC 6394/10  

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