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23S05T-1DCG PDF预览

23S05T-1DCG

更新时间: 2024-02-26 17:48:33
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管PC
页数 文件大小 规格书
6页 54K
描述
2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE

23S05T-1DCG 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-8
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.74
系列:23S输入调节:STANDARD
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.008 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:2.5 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns子类别:Clock Drivers
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL最小 fmax:133 MHz
Base Number Matches:1

23S05T-1DCG 数据手册

 浏览型号23S05T-1DCG的Datasheet PDF文件第2页浏览型号23S05T-1DCG的Datasheet PDF文件第3页浏览型号23S05T-1DCG的Datasheet PDF文件第4页浏览型号23S05T-1DCG的Datasheet PDF文件第5页浏览型号23S05T-1DCG的Datasheet PDF文件第6页 
IDT23S05T  
2.5V ZERO DELAY CLOCK  
BUFFER, SPREAD SPECTRUM  
COMPATIBLE  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 133MHz operating frequency  
• Distributes one clock input to one bank of five outputs  
• Zero Input-Output Delay  
The IDT23S05T is a high-speed phase-lock loop (PLL) clock buffer,  
designedtoaddresshigh-speedclockdistributionapplications. Thezero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 133MHz.  
• Output Skew < 250ps  
The IDT23S05T is an 8-pin version of the IDT23S09T. IDT23S05T  
acceptsonereferenceinput, anddrivesoutfivelowskewclocks. Allparts  
have on-chip PLLs which lock to an input clock on the REF pin. The PLL  
feedbackison-chipandisobtainedfromtheCLKOUTpad.Intheabsence  
of an input clock, the IDT23S05T enters power down. In this mode, the  
devicewilldraw lessthan12µA for Commercial Temperature Range and  
and less than 25µA for Industrial temperature range, the outputs are tri-  
stated, and the PLL is not running, resulting in a significant reduction of  
power. TheIDT23S05TischaracterizedforbothIndustrialandCommer-  
cialoperation.  
• Low jitter <200 ps cycle-to-cycle  
• No external RC network required  
• Operates at 2.5V VDD  
• Power down mode  
• Spread spectrum compatible  
• Available in SOIC package  
FUNCTIONALBLOCKDIAGRAM  
8
CLKOUT  
3
CLK1  
PLL  
1
Control  
Logic  
REF  
2
CLK2  
CLK3  
CLK4  
5
7
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
MAY 2010  
1
c
2006 Integrated Device Technology, Inc.  
DSC 6397/11  

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