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2308B-3DCGI PDF预览

2308B-3DCGI

更新时间: 2024-02-26 16:12:58
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
17页 399K
描述
Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, ROHS COMPLIANT, SOIC-16

2308B-3DCGI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.6系列:2308
输入调节:STANDARDJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:9.9314 mm
逻辑集成电路类型:CLOCK DRIVER最大I(ol):0.008 A
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:16
实输出次数:8最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.4 ns座面最大高度:1.7272 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.937 mm最小 fmax:133.3 MHz
Base Number Matches:1

2308B-3DCGI 数据手册

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DATASHEET  
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER  
IDT2308B  
Description  
Features  
The IDT2308B is a high-speed phase-lock loop (PLL) clock  
multiplier. It is designed to address high-speed clock  
distribution and multiplication applications. The zero delay  
is achieved by aligning the phase between the incoming  
clock and the output clock, operable within the range of 10  
to 133 MHz.  
Phase-Lock Loop Clock Distribution for Applications  
ranging from 10 MHz to 133 MHz operating frequency  
Distributes one clock input to two banks of four outputs  
Separate output enable for each output bank  
External feedback (FBK) pin is used to synchronize the  
outputs to the clock input  
The IDT2308B has two banks of four outputs each that are  
controlled via two select addresses. By proper selection of  
input addresses, both banks can be put in tri-state mode. In  
test mode, the PLL is turned off, and the input clock directly  
drives the outputs for system testing purposes. In the  
absence of an input clock, the IDT2308B enters power  
down, and the outputs are tri-stated. In this mode, the  
device will draw less than 25µA.  
Output Skew <200 ps  
Low jitter <200 ps cycle-to-cycle  
1x, 2x, 4x output options (see Available Options table)  
No external RC network required  
Operates at 3.3 V V  
DD  
Available in 16-pin SOIC and TSSOP packages  
The IDT2308B is available in six unique configurations for  
both prescaling and multiplication of the Input REF Clock.  
(see Available Options table.)  
Available in Commercial and Industrial temperature  
ranges  
The PLL is closed externally to provide more flexibility by  
allowing the user to control the delay between the input  
clock and the outputs.  
Block Diagram  
IDT™ 3.3 VOLT ZERO DELAY CLOCK MULTIPLIER  
1
IDT2308B  
REV B 030509  

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