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2305B-1DCG PDF预览

2305B-1DCG

更新时间: 2024-02-25 05:09:32
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管PC
页数 文件大小 规格书
10页 156K
描述
3.3V ZERO DELAY CLOCK BUFFER

2305B-1DCG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:SOP, TSSOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.64
系列:2305输入调节:STANDARD
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.008 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:TSSOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
最小 fmax:133 MHzBase Number Matches:1

2305B-1DCG 数据手册

 浏览型号2305B-1DCG的Datasheet PDF文件第2页浏览型号2305B-1DCG的Datasheet PDF文件第3页浏览型号2305B-1DCG的Datasheet PDF文件第4页浏览型号2305B-1DCG的Datasheet PDF文件第5页浏览型号2305B-1DCG的Datasheet PDF文件第6页浏览型号2305B-1DCG的Datasheet PDF文件第7页 
IDT2305B  
3.3V ZERO DELAY  
CLOCK BUFFER  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 133MHz operating frequency  
• Distributes one clock input to one bank of five outputs  
• Zero Input-Output Delay  
The IDT2305B is a high-speed phase-lock loop (PLL) clock buffer,  
designed to address high-speed clock distribution applications. The zero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 133MHz.  
• Output Skew < 250ps  
The IDT2305B is an 8-pin version of the IDT2309B. IDT2305B accepts  
one reference input, and drives out five low skew clocks. The -1H version  
of this device operates, up to 133MHz frequency and has a higher drive  
thanthe-1device. Allpartshaveon-chipPLLswhichlocktoaninputclock  
on the REF pin. The PLL feedback is on-chip and is obtained from the  
CLKOUTpad.Intheabsenceofaninputclock,theIDT2305Benterspower  
down. In this mode, the device will draw less than 25µA, the outputs are  
tri-stated, and the PLL is not running, resulting in a significant reduction of  
power.  
• Low jitter <175 ps cycle-to-cycle  
• 50ps typical cycle-to-cycle jitter (15pF, 66MHz)  
• IDT2305B-1 for Standard Drive  
• IDT2305B-1H for High Drive  
• No external RC network required  
• Operates at 3.3V VDD  
• Power down mode  
• Available in SOIC and TSSOP packages  
The IDT2305B is characterized for both Industrial and Commercial  
operation.  
NOTE: EOL for non-green parts to occur on 5/13/10 per  
PDNU-09-01  
FUNCTIONALBLOCKDIAGRAM  
8
CLKOUT  
3
CLK1  
PLL  
1
Control  
Logic  
REF  
2
CLK2  
CLK3  
CLK4  
5
7
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
AUGUST 2009  
1
c
2007 Integrated Device Technology, Inc.  
DSC 6994/5  

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