5秒后页面跳转
2305-1HDCI PDF预览

2305-1HDCI

更新时间: 2024-01-27 19:29:32
品牌 Logo 应用领域
艾迪悌 - IDT RC网络时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
12页 186K
描述
3.3V ZERO DELAY CLOCK BUFFER No external RC network required

2305-1HDCI 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-8
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5
Is Samacsys:N系列:2305
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.9 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.012 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V传播延迟(tpd):0.35 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.75 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mm最小 fmax:133 MHz
Base Number Matches:1

2305-1HDCI 数据手册

 浏览型号2305-1HDCI的Datasheet PDF文件第2页浏览型号2305-1HDCI的Datasheet PDF文件第3页浏览型号2305-1HDCI的Datasheet PDF文件第4页浏览型号2305-1HDCI的Datasheet PDF文件第5页浏览型号2305-1HDCI的Datasheet PDF文件第6页浏览型号2305-1HDCI的Datasheet PDF文件第7页 
IDT2305  
3.3V ZERO DELAY  
CLOCK BUFFER  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 133MHz operating frequency  
• Distributes one clock input to one bank of five outputs  
• Zero Input-Output Delay  
The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer,  
designed to address high-speed clock distribution applications. The zero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 133MHz.  
• Output Skew < 250ps  
The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one  
referenceinput,anddrivesoutfivelowskewclocks.The-1Hversionofthis  
device operates, up to 133MHz frequency and has a higher drive than the  
-1 device. All parts have on-chip PLLs which lock to an input clock on the  
REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT  
pad. In the absence of an input clock, the IDT2305 enters power down. In  
• Low jitter <200 ps cycle-to-cycle  
• IDT2305-1 for Standard Drive  
• IDT2305-1H for High Drive  
• No external RC network required  
• Operates at 3.3V VDD  
• Power down mode  
• Available in SOIC/TSSOP packages  
this mode, the device will draw less than 25µA, the outputs are tri-stated,  
and the PLL is not running, resulting in a significant reduction of power.  
The IDT2305 is characterized for both Industrial and Commercial  
NOTE: EOL for non-green parts to occur on  
5/13/10 per PDN U-09-01  
operation.  
FUNCTIONALBLOCKDIAGRAM  
8
CLKOUT  
3
CLK1  
PLL  
1
Control  
Logic  
REF  
2
CLK2  
CLK3  
CLK4  
5
7
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
AUGUST 2009  
1
c
2009 Integrated Device Technology, Inc.  
DSC 5174/8  

与2305-1HDCI相关器件

型号 品牌 描述 获取价格 数据表
2305-1HDCI8 IDT PLL Based Clock Driver, 2305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, SOIC-8

获取价格

2305-1PGG IDT 3.3V ZERO DELAY CLOCK BUFFER No external RC network required

获取价格

2305-1PGGI IDT 3.3V ZERO DELAY CLOCK BUFFER No external RC network required

获取价格

2305-2 KR Bandpass Filter

获取价格

2305-2-00-44-00-00-07-0 MILL-MAX PCB Terminal, PFOA, PFOS, ROHS AND REACH COMPLIANT

获取价格

2305-21-D1-30-010 ECS Card Edge Connector

获取价格