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1894K-32LF PDF预览

1894K-32LF

更新时间: 2024-01-24 18:13:17
品牌 Logo 应用领域
艾迪悌 - IDT 网络接口电信集成电路电信电路PC
页数 文件大小 规格书
50页 306K
描述
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

1894K-32LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:VFQFPN
包装说明:HVQCCN, LCC32,.2SQ,20针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.49
Samacsys Confidence:4Samacsys Status:Released
2D Presentation:https://componentsearchengine.com/2D/0T/11129679.2.1.pngSchematic Symbol:https://componentsearchengine.com/symbol.php?partID=11129679
PCB Footprint:https://componentsearchengine.com/footprint.php?partID=111296793D View:https://componentsearchengine.com/viewer/3D.php?partID=11129679
Samacsys PartID:11129679Samacsys Image:https://componentsearchengine.com/Images/9/1894K-32LFT.jpg
Samacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/2/1894K-32LFT.jpgSamacsys Pin Count:33
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Quad Flat No-Lead
Samacsys Footprint Name:NLG32P1Samacsys Released Date:2020-01-28 13:44:07
Is Samacsys:N数据速率:100000 Mbps
JESD-30 代码:S-XQCC-N32JESD-609代码:e3
长度:5 mm湿度敏感等级:3
功能数量:1端子数量:32
收发器数量:1最高工作温度:70 °C
最低工作温度:封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC32,.2SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:Network Interfaces标称供电电压:3.3 V
表面贴装:YES技术:CMOS
电信集成电路类型:INTERFACE CIRCUIT温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:5 mm
Base Number Matches:1

1894K-32LF 数据手册

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DATASHEET  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
ICS1894-32  
Description  
Features  
The ICS1894-32 is a low-power, physical-layer device  
(PHY) that supports the ISO/IEC 10Base-T and  
100Base-TX Carrier-Sense Multiple Access/Collision  
Detection (CSMA/CD) Ethernet standards, ISO/IEC  
8802.3. It is intended for RMII/MII Node applications and  
includes the Auto-MDIX feature that automatically corrects  
crossover errors in plant wiring.  
Supports category 5 cables and above with attenuation in  
excess of 24dB at 100 MHz.  
Single-chip, fully integrated PHY provides PCS, PMA,  
PMD, and AUTONEG sub layers functions of IEEE  
standard.  
10Base-T and 100Base-TX ISO/IEC 8802.3 compliant  
MIIM (MDC/MDIO) management bus for PHY register  
The ICS1894-32 incorporates Digital-Signal Processing  
(DSP) control in its Physical-Medium Dependent (PMD)  
sub-layer. As a result, it can transmit and receive data on  
unshielded twisted-pair (UTP) category 5 cables with  
attenuation in excess of 24 dB at 100MHz.  
configuration  
RMII interface support with external 50 MHz system clock  
Single 3.3V power supply  
Highly configurable, supports:  
The ICS1894-32 provides a Serial-Management Interface  
for exchanging command and status information with a  
Station-Management (STA) entity. The ICS1894-32  
Media-Dependent Interface (MDI) can be configured to  
provide full-duplex operation at data rates of 10 Mb/s or  
100Mb/s.  
– Media Independent Interface (MII)  
– Auto-Negotiation with Parallel detection  
– Node applications, managed or unmanaged  
– 10M or 100M full duplex modes  
– Loopback mode for Diagnostic Functions  
Auto-MDI/MDIX crossover correction  
Low-power CMOS (typically 300 mW)  
Power-Down mode (typically 21mW)  
Clock and crystal supported in MII mode  
Programmable LEDs  
In addition, the ICS1894-32 includes a programmable LED  
and interrupt output function. The LED outputs can be  
configured through registers to indicate the occurance of  
certain events such as LINK, COLLISION, ACTIVITY, etc.  
The purpose of the programmable interrupt output is to  
notify the PHY controller device immediately when a certain  
event happens instead of having the PHY controller  
continuously poll the PHY. The events that could be used to  
generate interrupts are: receiver error, Jabber, page  
received, parallel detect fault, link partner acknowledge, link  
status change, auto-negotiation complete, remote fault,  
collision, etc.  
Interrupt output pin  
Fully integrated, DSP-based PMD includes:  
– Adaptive equalization and baseline-wander  
correction  
The ICS1894-32 has deep power modes that can result in  
significant power savings when the link is broken.  
Transmit wave shaping and stream cipher  
scrambler  
– MLT-3 encoder and NRZ/NRZI encoder  
Core power supply (3.3 V)  
Applications: NIC cards, PC motherboards, switches,  
routers, DSL and cable modems, game machines, printers,  
network connected appliances, and industrial equipment.  
3.3 V/1.8 V VDDIO operation supported  
Smart power control with deep power down feature  
Available in 32-pin (5mm x 5mm) QFN package, Pb-free  
Available in Industrial Temp and Lead Free  
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
1
ICS1894-32  
REV K 060110  

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