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180M-02LFT PDF预览

180M-02LFT

更新时间: 2024-01-19 08:46:34
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
7页 136K
描述
Clock Generator, CMOS, PDSO8

180M-02LFT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
Reach Compliance Code:compliant风险等级:5.84
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
湿度敏感等级:1端子数量:8
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:3.3/5 V
认证状态:Not Qualified子类别:Clock Generators
最大压摆率:50 mA表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

180M-02LFT 数据手册

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DATASHEET  
LOW EMI CLOCK GENERATOR  
ICS180-02  
Description  
Features  
The ICS180-02 generates a low EMI output clock from  
a clock or crystal input. The device uses ICS’  
proprietary mix of analog and digital Phase-Locked  
Loop (PLL) technology to spread the frequency  
spectrum of the output, thereby reducing the frequency  
amplitude peaks by several dB.  
Pin and function compatible to Cypress W180-02  
Packaged in 8-pin SOIC  
Provides a spread spectrum output clock  
Accepts a clock input and provides same frequency  
dithered output  
Input frequency of 8 to 15 MHz  
The ICS180-02 offers down spread selection of -1.25%  
and -3.75%. Refer to the MK1714-01/02 for the widest  
selection of input frequencies and multipliers.  
Peak reduction by 7dB - 14dB typical on 3rd - 19th  
odd harmonics  
Spread percentage selection for -1.25% and -3.75%  
Operating voltage of 3.3 V and 5 V  
ICS offers a complete line of EMI reducing clock  
generators. Consult us when you need to remove  
crystals and oscillators from your board.  
Advanced, low-power CMOS process  
Block Diagram  
VDD  
FS1  
SSON#  
PLL Clock  
Synthesis  
SS%  
and Spread  
Spectrum  
Circuitry  
CLK  
X1/CLKIN  
Clock Buffer/  
Crystal  
Oscillator  
X2  
GND  
IDT™ / ICS™ LOW EMI CLOCK GENERATOR  
1
ICS180-02  
REV A 110404  

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