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1527G-60LF PDF预览

1527G-60LF

更新时间: 2024-02-09 06:49:30
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
11页 92K
描述
PLL Based Clock Driver, 1527 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, 0.65 MM PITCH, LEAD FREE, TSSOP-16

1527G-60LF 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:4.40 MM, 0.65 MM PITCH, LEAD FREE, TSSOP-16
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.71
系列:1527输入调节:SCHMITT TRIGGER
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:5 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:16
实输出次数:2最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):10 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):1 ns座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
最小 fmax:60 MHzBase Number Matches:1

1527G-60LF 数据手册

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ICS1527  
Video Clock Synthesizer  
General Description  
Features  
• Lead-free packaging (Pb-free)  
The ICS1527 is a low-cost, high-performance  
frequency generator. It is suited to general purpose  
phase controlled clock synthesis as well as  
line-locked and genlocked high-resolution video  
applications. Using ICS’s advanced low-voltage  
CMOS mixed-mode technology, the ICS1527 is an  
effective clock synthesizer that supports video  
projectors and displays at resolutions from VGA to  
beyond XGA.  
• Low jitter (typical 27 ps short term jitter)  
• LVCMOS single-ended clock outputs  
• 60/110 MHz speed grades available  
• Uses 3.3 V power supply  
• 5 Volt tolerant Inputs (HSYNC, VSYNC)  
• Coast (ignore HSYNC) capability via VSYNC pin  
2
• Industry standard I C-bus programming interface  
The ICS1527 offers single-ended clock outputs to 60  
or 110 MHz. The HSYNC_out, and VSYNC_out pins  
provide the regenerated versions of the HSYNC and  
VSYNC inputs synchronous to the CLK output.  
2
• PLL Lock detection via I C or LOCK output pin  
• 16-pin TSSOP package  
Applications  
The advanced PLL uses either its internal  
programmable feedback divider or an external divider.  
The device is programmed by a standard I2C-bus™  
serial interface and is available in a TSSOP16  
package.  
• Frequency synthesis  
• LCD monitors, video projectors and plasma displays  
• Genlocking multiple video subsystems  
Pin Configuration (16-pin TSSOP)  
ICS1527 Functional Diagram  
VSSD  
SDA  
SCL  
VSYNC  
EXTFB  
HSYNC  
VDDA  
VSSA  
VDDD  
VSSQ  
VSYNC_out  
VDDQ  
CLK  
HSYNC_out  
LOCK  
I2CADR  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
HSYNC  
VSYNC  
I2C  
HSYNC_out  
VSYNC_out  
ICS1527  
CLK  
EXTFB  
External  
Divider  
MDS 1527 G  
Revision 110905  
IDT reserves the right to make changes in the preliminary device data  
identified in this publication without notice. IDT advises its customers  
to obtain the latest version of all device data to verify that information  
being relied upon is current and accurate.  

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