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IC41C82052-50J PDF预览

IC41C82052-50J - INTEGRATED CIRCUIT SOLUTION INC

内存集成电路光电二极管动态存储器
型号:
IC41C82052-50J
Datasheet下载:
下载Datasheet文件
产品描述:
2M x 8 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
应用标签:
内存集成电路光电二极管动态存储器
文档页数/大小:
18页 / 195K
品牌Logo:
品牌名称:
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]

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IC41C82052-50J

应用: 内存集成电路光电二极管动态存储器

文档: 18页 / 195K

品牌: ICSI

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  • 参数详情
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是否Rohs认证
不符合
生命周期
Transferred
IHS 制造商
INTEGRATED CIRCUIT SOLUTION INC
包装说明
SOJ, SOJ28,.34
Reach Compliance Code
unknown
风险等级
5.83
Is Samacsys
N
最长访问时间
50 ns
I/O 类型
COMMON
JESD-30 代码
R-PDSO-J28
JESD-609代码
e0
内存密度
16777216 bit
内存集成电路类型
FAST PAGE DRAM
内存宽度
8
端子数量
28
字数
2097152 words
字数代码
2000000
最高工作温度
70 °C
最低工作温度
组织
2MX8
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
SOJ
封装等效代码
SOJ28,.34
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
电源
5 V
认证状态
Not Qualified
刷新周期
2048
自我刷新
NO
最大待机电流
0.001 A
子类别
DRAMs
最大压摆率
0.12 mA
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
J BEND
端子节距
1.27 mm
端子位置
DUAL
Base Number Matches
1
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IC41C82052
IC41LV82052
2M x 8 (16-MBIT) DYNAMIC RAM
WITH .AST PAGE MODE
.EATURES
• .AST Page Mode access cycle
• TTL compatible inputs and outputs
• Refresh Interval:
-- 2,048 cycles/32 ms
• Refresh Mode:
4)5-Only,
+)5-before-4)5
(CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
5V±10% or 3.3V ± 10%
• Byte Write and Byte Read operation via
+)5
DESCRIPTION
The
1+51
82052 Series is a 2,097,152 x 8-bit high-performance
CMOS Dynamic Random Access Memory. The .ast Page
Mode allows 2,048 random accesses within a single row with
access cycle time as short as 20 ns per 8-bit word.
These features make the 82052 Series ideally suited for high-
bandwidth graphics, digital signal processing, high-performance
computing systems, and peripheral applications.
The 82052 Series is packaged in a 28-pin 300mil SOJ and a 28
pin TSOP-2
PRODUCT SERIES OVERVIEW
Part No.
IC41C82052
IC41LV82052
Refresh
2K
2K
Voltage
5V ± 10%
3.3V ± 10%
KEY TIMING PARAMETERS
Parameter
RAS
Access Time (t
RAC
)
CAS
Access Time (t
CAC
)
Column Address Access Time (t
AA
)
EDO Page Mode Cycle Time (t
PC
)
Read/Write Cycle Time (t
RC
)
-50
50
13
25
20
84
-60
60
15
30
25
104
Unit
ns
ns
ns
ns
ns
PIN CON.IGURATION
28 Pin SOJ, TSOP-2
VCC
I/O0
I/O1
I/O2
I/O3
WE
RAS
NC
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
I/O7
I/O6
I/O5
I/O4
CAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A10
I/O0-7
WE
OE
RAS
CAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR015-0A 06/12/2001
1

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