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MK1707DLFTR PDF预览

MK1707DLFTR

更新时间: 2024-01-11 01:43:26
品牌 Logo 应用领域
矽成 - ICSI 晶体时钟发生器外围集成电路光电二极管
页数 文件大小 规格书
7页 135K
描述
Low EMI Clock Generator

MK1707DLFTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOIC-8针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.67
系列:1707输入调节:STANDARD
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:8实输出次数:1
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:3.3/5 V认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Clock Drivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
最小 fmax:167 MHzBase Number Matches:1

MK1707DLFTR 数据手册

 浏览型号MK1707DLFTR的Datasheet PDF文件第2页浏览型号MK1707DLFTR的Datasheet PDF文件第3页浏览型号MK1707DLFTR的Datasheet PDF文件第4页浏览型号MK1707DLFTR的Datasheet PDF文件第5页浏览型号MK1707DLFTR的Datasheet PDF文件第6页浏览型号MK1707DLFTR的Datasheet PDF文件第7页 
MK1707D  
Low EMI Clock Generator  
Description  
Features  
The MK1707D generates a low EMI output clock from a  
crystal clock input. The part is designed to dither the  
LCD interface clock for flat panel graphics controllers.  
The device uses ICS’ proprietary mix of analog and  
digital Phase-Locked Loop (PLL) technology to spread  
the frequency spectrum of the output, thereby reducing  
the frequency amplitude peaks by several dB.  
Packaged in 8-pin SOIC  
Available in Pb (lead) free package  
Provides a spread spectrum output clock  
Supports flat panel controllers  
Accepts a crystal or clock input to provide same  
frequency dithered output  
Input operating frequencies of 25-54 and 50-108  
MHz  
The MK1707D offers centered spread from a wide  
range of input clock frequencies.  
Peak reduction by 7dB to 14dB typical on 3rd through  
ICS offers many other clocks for computers and  
computer peripherals. Consult ICS when you need to  
replace multiple crystals and oscillators from your  
board.  
19th odd harmonics  
Low EMI feature can be disabled  
Includes power down  
Operating voltage of 3.3 V  
Industrial temperature range available  
Advanced, low-power CMOS process  
Block Diagram  
VDD  
2
S1:0  
Low EMI Enable  
PLL Clock  
Synthesis  
and Spread  
Spectrum  
Circuitry  
Clock Out  
X1/ICLK  
Input  
Buffer  
X2  
Load capacitors required  
for crystal input  
GND  
MDS 1707D F  
1
Revision 102804  
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  

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