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HY57V561620LT-8 PDF预览

HY57V561620LT-8

更新时间: 2024-02-15 04:14:50
品牌 Logo 应用领域
海力士 - HYNIX 存储内存集成电路光电二极管动态存储器时钟
页数 文件大小 规格书
13页 153K
描述
4Banks x 4M x 16Bit Synchronous DRAM

HY57V561620LT-8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2, TSOP54,.46,32针数:54
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.24风险等级:5.79
Is Samacsys:N访问模式:FOUR BANK PAGE BURST
最长访问时间:6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):125 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PDSO-G54
长度:22.22 mm内存密度:268435456 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:54字数:16777216 words
字数代码:16000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP54,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
刷新周期:8192座面最大高度:1.2 mm
自我刷新:YES连续突发长度:1,2,4,8,FP
最大待机电流:0.002 A子类别:DRAMs
最大压摆率:0.26 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

HY57V561620LT-8 数据手册

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HY57V561620(L)T  
4Banks x 4M x 16Bit Synchronous DRAM  
DESCRIPTION  
The HY57V561620T is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications  
which require large memory density and high bandwidth. HY57V561620 is organized as 4 banks of 4,194,304x16.  
The HY57V561620T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and  
outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very  
high bandwidth. All input and output voltage levels are compatible with LVTTL.  
Programmable options include the length of pipeline ( CAS latency of 2 or 3), the number of consecutive read or write  
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count  
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate  
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined  
design is not restricted by a `2N` rule.)  
FEATURES  
Single 3.3V ± 0.3V power supply  
Auto refresh and self refresh  
All device pins are compatible with LVTTL interface  
8192 refresh cycles / 64ms  
JEDEC standard 400mil 54pin TSOP-II with 0.8mm  
of pin pitch  
Programmable Burst Length and Burst Type  
- 1, 2, 4, 8 and Full Page for Sequential Burst  
- 1, 2, 4 and 8 for Interleave Burst  
Programmable CAS Latency ; 2, 3 Clocks  
All inputs and outputs referenced to positive edge of  
system clock  
Data mask function by UDQM and LDQM  
Internal four banks operation  
ORDERING INFORMATION  
Part No.  
Clock Frequency  
Power  
Organization  
Interface  
Package  
HY57V561620T-HP  
HY57V561620T-H  
HY57V561620T-8  
HY57V561620T-P  
HY57V561620T-S  
HY57V561620LT-HP  
HY57V561620LT-H  
HY57V561620LT-8  
HY57V561620LT-P  
HY57V561620LT-S  
133MHz  
133MHz  
125MHz  
100MHz  
100MHz  
133MHz  
133MHz  
125MHz  
100MHz  
100MHz  
Normal  
4Banks x 4Mbits  
x16  
LVTTL  
400mil 54pin TSOP II  
Lower  
Power  
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Revision 1.8 / Apr.01  

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