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GM71VS18163CLJ-6 PDF预览

GM71VS18163CLJ-6

更新时间: 2024-01-25 09:42:18
品牌 Logo 应用领域
海力士 - HYNIX 内存集成电路光电二极管动态存储器
页数 文件大小 规格书
11页 115K
描述
x16 EDO Page Mode DRAM

GM71VS18163CLJ-6 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:5.7
Is Samacsys:N访问模式:FAST PAGE WITH EDO
最长访问时间:60 ns其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH/BATTERY BACKUP/SELF REFRESH
JESD-30 代码:R-PDSO-J42内存密度:16777216 bit
内存集成电路类型:EDO DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:42字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1MX16封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
认证状态:Not Qualified自我刷新:YES
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:J BEND端子位置:DUAL
Base Number Matches:1

GM71VS18163CLJ-6 数据手册

 浏览型号GM71VS18163CLJ-6的Datasheet PDF文件第2页浏览型号GM71VS18163CLJ-6的Datasheet PDF文件第3页浏览型号GM71VS18163CLJ-6的Datasheet PDF文件第4页浏览型号GM71VS18163CLJ-6的Datasheet PDF文件第5页浏览型号GM71VS18163CLJ-6的Datasheet PDF文件第6页浏览型号GM71VS18163CLJ-6的Datasheet PDF文件第7页 
GM71V18163C  
GM71VS18163CL  
1,048,576 WORDS x 16 BIT  
CMOS DYNAMIC RAM  
Description  
Features  
The GM71V(S)18163C/CL is the new  
generation dynamic RAM organized 1,048,576  
x 16 bit. GM71V(S)18163C/CL has realized  
higher density, higher performance and various  
functions by utilizing advanced CMOS process  
technology. The GM71V(S)18163C/CL offers  
Extended Data out(EDO) Mode as a high speed  
access mode. Multiplexed address inputs permit  
the GM71V(S)18163C/CL to be packaged in  
standard 400 mil 42pin plastic SOJ, and standard  
400mil 44(50)pin plastic TSOP II. The package  
size provides high system bit densities and is  
compatible with widely available automated  
testing and insertion equipment.  
* 1,048,576 Words x 16 Bit Organization  
* Extended Data Out Mode Capability  
* Single Power Supply (3.3V+/-0.3V)  
* Fast Access Time & Cycle Time  
(Unit: ns)  
tRAC  
tCAC  
tRC  
tHPC  
50  
60  
70  
13  
15 104  
18 124  
84  
20  
25  
30  
GM71V(S)18163C/CL-5  
GM71V(S)18163C/CL-6  
GM71V(S)18163C/CL-7  
* Low Power  
Active : 684/612/540mW (MAX)  
Standby : 7.2mW (CMOS level : MAX)  
0.83mW (L-version : MAX)  
* RAS Only Refresh, CAS before RAS Refresh,  
Hidden Refresh Capability  
* All inputs and outputs TTL Compatible  
* 1024 Refresh Cycles/16ms  
* 1024 Refresh Cycles/128ms (L-version)  
* Self Refresh Operation (L-version)  
* Battery Back Up Operation (L-version)  
* 2 CAS byte Control  
Pin Configuration  
42 SOJ  
44(50) TSOP II  
1
VSS  
50  
VCC  
1
42  
41  
VSS  
VCC  
I/O0  
I/O1  
I/O2  
I/O3  
VCC  
49  
2
3
4
5
6
7
8
9
I/O0  
I/O1  
I/O2  
I/O3  
VCC  
I/O4  
I/O5  
I/O6  
I/O7  
NC  
I/O15  
I/O14  
I/O13  
2
3
4
5
6
I/O15  
48  
47  
40 I/O14  
39 I/O13  
46 I/O12  
45 VSS  
38  
I/O12  
37  
VSS  
44  
I/O11  
7
36  
I/O11  
I/O4  
I/O5  
I/O6  
I/O7  
NC  
43 I/O10  
42 I/O9  
41 I/O8  
8
35  
I/O10  
10  
11  
9
34  
33  
32  
31  
30  
29  
28  
I/O9  
I/O8  
NC  
40  
NC  
10  
11  
12  
13  
14  
15  
LCAS  
UCAS  
OE  
NC  
WE  
RAS  
NC  
NC  
NC  
36 NC  
15  
16  
35  
LCAS  
34  
17  
18  
WE  
UCAS  
33  
RAS  
A9  
OE  
32  
A9  
A8  
A7  
A6  
19  
A11  
A10  
A0  
A1  
A2  
16  
17  
18  
19  
20  
21  
27  
A8  
NC  
31  
20  
21  
22  
23  
26 A7  
A0  
30  
25  
A6  
A1  
A2  
29  
24  
A5  
28 A5  
27 A4  
23 A4  
A3  
24  
25  
A3  
VCC  
26  
22  
VSS  
VCC  
VSS  
(Top View)  
Rev 0.1 / Apr’01  

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