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GM71V17403CLJ-6 PDF预览

GM71V17403CLJ-6

更新时间: 2024-02-07 06:42:29
品牌 Logo 应用领域
海力士 - HYNIX 动态存储器光电二极管
页数 文件大小 规格书
10页 96K
描述
EDO DRAM, 4MX4, 60ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-26/24

GM71V17403CLJ-6 技术参数

生命周期:Obsolete包装说明:SOJ,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.21
访问模式:FAST PAGE WITH EDO最长访问时间:60 ns
其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN/BATTERY BACKUP REFRESHJESD-30 代码:R-PDSO-J24
长度:16.9 mm内存密度:16777216 bit
内存集成电路类型:EDO DRAM内存宽度:4
功能数量:1端口数量:1
端子数量:24字数:4194304 words
字数代码:4000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4MX4封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
座面最大高度:3.75 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

GM71V17403CLJ-6 数据手册

 浏览型号GM71V17403CLJ-6的Datasheet PDF文件第2页浏览型号GM71V17403CLJ-6的Datasheet PDF文件第3页浏览型号GM71V17403CLJ-6的Datasheet PDF文件第4页浏览型号GM71V17403CLJ-6的Datasheet PDF文件第5页浏览型号GM71V17403CLJ-6的Datasheet PDF文件第6页浏览型号GM71V17403CLJ-6的Datasheet PDF文件第7页 
GM71V17403C  
GM71VS17403CL  
4,194,304 WORDS x 4 BIT  
CMOS DYNAMIC RAM  
Description  
Features  
* 4,194,304 Words x 4 Bit Organization  
* Extended Data Out Mode Capability  
* Single Power Supply (3.3V +/- 0.3V)  
* Fast Access Time & Cycle Time  
The GM71V(S)17403C/CL is the new  
generation dynamic RAM organized 4,194,304  
words x 4 bit. GM71V(S)17403C/CL has  
realized higher density, higher performance and  
various functions by utilizing advanced CMOS  
process technology. The GM71V(S)17403C/CL  
offers Extended Data Out (EDO) Page Mode as  
a high speed access mode. Multiplexed address  
inputs permit the GM71V(S)17403C/CL to be  
packaged in a standard 300 mil 24(26) pin SOJ,  
and a standard 300 mil 24(26) pin plastic TSOP  
II. The package size provides high system bit  
densities and is compatible with widely  
available automated testing and insertion  
equipment. System oriented features include  
single power supply 3.3V +/- 0.3V tolerance,  
direct interfacing capability with high  
performance logic families such as Schottky  
TTL.  
(Unit: ns)  
tRAC  
tCAC  
tRC  
tHPC  
50  
60  
70  
13  
15 104  
18 124  
84  
20  
25  
30  
GM71V(S)17403C/CL-5  
GM71V(S)17403C/CL-6  
GM71V(S)17403C/CL-7  
* Low Power  
Active : 432/369/360mW (MAX)  
Standby : 7.2mW (CMOS level : MAX)  
: 0.36mW (L-version : MAX)  
* RAS Only Refresh, CAS before RAS Refresh,  
Hidden Refresh Capability  
*All inputs and outputs TTL Compatible  
* 2048 Refresh Cycles/32ms  
* 2048 Refresh Cycles/128ms (L-version)  
* Self Refresh Operation (L-version)  
* Battery Backup Operation (L-version)  
* Test Function : 16bit parallel test mode  
Pin Configuration  
24(26) SOJ  
24(26) TSOP II  
1
26  
VCC  
I/O1  
I/O2  
WE  
VSS  
1
26  
VCC  
I/O1  
I/O2  
WE  
VSS  
2
3
25  
24  
I/O4  
I/O3  
CAS  
OE  
2
3
4
5
6
25  
24  
23  
22  
21  
I/O4  
I/O3  
CAS  
OE  
4
5
6
23  
22  
21  
RAS  
NC  
RAS  
A11  
A9  
A9  
8
19  
18  
17  
16  
15  
14  
A10  
A0  
A8  
A7  
A6  
A5  
A4  
VSS  
8
9
19  
18  
A10  
A0  
A8  
A7  
A6  
A5  
A4  
VSS  
9
10  
11  
12  
13  
A1  
10  
11  
12  
13  
17  
16  
15  
14  
A1  
A2  
A2  
A3  
A3  
VCC  
VCC  
(Top View)  
Rev 0.1 / Apr’01  

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