GM71V17403C
GM71VS17403CL
4,194,304 WORDS x 4 BIT
CMOS DYNAMIC RAM
Description
Features
* 4,194,304 Words x 4 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (3.3V +/- 0.3V)
* Fast Access Time & Cycle Time
The GM71V(S)17403C/CL is the new
generation dynamic RAM organized 4,194,304
words x 4 bit. GM71V(S)17403C/CL has
realized higher density, higher performance and
various functions by utilizing advanced CMOS
process technology. The GM71V(S)17403C/CL
offers Extended Data Out (EDO) Page Mode as
a high speed access mode. Multiplexed address
inputs permit the GM71V(S)17403C/CL to be
packaged in a standard 300 mil 24(26) pin SOJ,
and a standard 300 mil 24(26) pin plastic TSOP
II. The package size provides high system bit
densities and is compatible with widely
available automated testing and insertion
equipment. System oriented features include
single power supply 3.3V +/- 0.3V tolerance,
direct interfacing capability with high
performance logic families such as Schottky
TTL.
(Unit: ns)
tRAC
tCAC
tRC
tHPC
50
60
70
13
15 104
18 124
84
20
25
30
GM71V(S)17403C/CL-5
GM71V(S)17403C/CL-6
GM71V(S)17403C/CL-7
* Low Power
Active : 432/369/360mW (MAX)
Standby : 7.2mW (CMOS level : MAX)
: 0.36mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
*All inputs and outputs TTL Compatible
* 2048 Refresh Cycles/32ms
* 2048 Refresh Cycles/128ms (L-version)
* Self Refresh Operation (L-version)
* Battery Backup Operation (L-version)
* Test Function : 16bit parallel test mode
Pin Configuration
24(26) SOJ
24(26) TSOP II
1
26
VCC
I/O1
I/O2
WE
VSS
1
26
VCC
I/O1
I/O2
WE
VSS
2
3
25
24
I/O4
I/O3
CAS
OE
2
3
4
5
6
25
24
23
22
21
I/O4
I/O3
CAS
OE
4
5
6
23
22
21
RAS
NC
RAS
A11
A9
A9
8
19
18
17
16
15
14
A10
A0
A8
A7
A6
A5
A4
VSS
8
9
19
18
A10
A0
A8
A7
A6
A5
A4
VSS
9
10
11
12
13
A1
10
11
12
13
17
16
15
14
A1
A2
A2
A3
A3
VCC
VCC
(Top View)
Rev 0.1 / Apr’01