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GM71C4400CR-70 PDF预览

GM71C4400CR-70

更新时间: 2024-02-26 16:38:53
品牌 Logo 应用领域
海力士 - HYNIX 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
9页 103K
描述
Fast Page DRAM, 1MX4, 70ns, CMOS, PDSO20,

GM71C4400CR-70 技术参数

是否Rohs认证:不符合生命周期:Active
包装说明:TSOP, TSOP20/26,.36Reach Compliance Code:compliant
风险等级:5.75Is Samacsys:N
最长访问时间:70 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
内存密度:4194304 bit内存集成电路类型:FAST PAGE DRAM
内存宽度:4端子数量:20
字数:1048576 words字数代码:1000000
最高工作温度:70 °C最低工作温度:
组织:1MX4输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP
封装等效代码:TSOP20/26,.36封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE电源:5 V
认证状态:Not Qualified刷新周期:1024
反向引出线:YES自我刷新:NO
最大待机电流:0.001 A子类别:DRAMs
最大压摆率:0.1 mA标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

GM71C4400CR-70 数据手册

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GM71C(S)4400C/CL  
1,048,576 WORDS x 4BIT  
LG Semicon Co.,Ltd.  
CMOS DYNAMIC RAM  
Description  
Features  
The GM71C(S)4400C/CL is the new generation  
dynamic RAM organized 1,048,576 words x 4 bit.  
GM71C(S)4400C/CL has realized higher density,  
higher performance and various functions by  
utilizing advanced CMOS process technology. The  
GM71C(S)4400C/CL offers Fast Page Mode as a  
high speed access Mode. Multiplexed address  
inputs permit the GM71C(S)4400C/CL to be  
packaged in a standard 300mil 20(26) pin plastic  
SOJ and standard 300mil 20(26) pin plastic  
TSOP II. The package size provides high system  
bit densities and is compatible with widely  
available automated testing and insertion  
equipment. System oriented features include single  
power supply of 5V+/-10% tolerance, direct  
interfacing capability with high performance logic  
families such as Schottky TTL.  
* 1,048,576 Words x 4 Bit Organization  
* Fast Page Mode Capability  
* Single Power Supply (5V+/-10%)  
* Fast Access Time & Cycle Time  
(Unit: ns)  
t
RAC  
60  
t
CAC  
15  
t
RC  
t
PC  
110  
130  
150  
40  
45  
50  
GM71C(S)4400C/CL-60  
GM71C(S)4400C/CL-70  
GM71C(S)4400C/CL-80  
70  
20  
80  
20  
* Low Power  
Active : 605/550/495mW (MAX)  
Standby : 5.5mW (CMOS level : MAX)  
1.1mW (L-version)  
* RAS Only Refresh, CAS before RAS Refresh,  
Hidden Refresh Capability  
* All inputs and outputs TTL Compatible  
* 1024 Refresh Cycles/16ms  
* 1024 Refresh Cycles/128ms (L-version)  
* Battery Back Up Operation (L-version)  
Pin Configuration  
20 (26) SOJ  
20 (26) TSOP II  
I/O1  
VSS  
I/O1  
1
2
3
4
5
20 VSS  
VSS 20  
1
2
3
4
5
I/O1  
19  
19  
I/O2  
WE  
RAS  
A9  
I/O4  
I/O3  
CAS  
OE  
I/O2  
WE  
RAS  
A9  
I/O4  
I/O4  
I/O2  
WE  
RAS  
A9  
18 I/O3  
I/O3 18  
17  
17  
CAS  
CAS  
16 OE  
OE 16  
A0  
A1  
6
7
15 A8  
A0  
A1  
6
7
15 A8  
A8 15  
6
7
A0  
A1  
14  
13  
14  
14  
A7  
A6  
A7  
A7  
8
8
13  
13  
8
A2  
A2  
A6  
A6  
A2  
A3  
9
12 A5  
A3  
9
12 A5  
A5 12  
9
A3  
10  
11  
10  
11  
11  
10  
VCC  
A4  
VCC  
A4  
A4  
VCC  
NORMAL TYPE  
REVERSE TYPE  
(Top View)  
(Top View)  
1

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