Datasheet > GM16C550-40

GM16C550-40

更新时间： 2024-02-29 13:11:35

品牌	Logo	应用领域
海力士 - HYNIX		通信时钟数据传输光电二极管外围集成电路
页数	文件大小	规格书
22页	205K
描述
Serial I/O Controller, 1 Channel(s), 0.0068359375MBps, CMOS, PDIP40, DIP-40

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技术参数
数据手册

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GM16C550-40 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP,	针数：	40
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.74	地址总线宽度：	3
边界扫描：	NO	最大时钟频率：	8 MHz
通信协议：	ASYNC, BIT	最大数据传输速率：	0.0068359375 MBps
外部数据总线宽度：	8	JESD-30 代码：	R-PDIP-T40
长度：	52.324 mm	低功率模式：	NO
串行 I/O 数：	1	端子数量：	40
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
认证状态：	Not Qualified	座面最大高度：	5.08 mm
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	宽度：	15.24 mm
uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	Base Number Matches：	1

GM16C550-40 数据手册

GM16C550

ASYNCHRONOUS COMMUNICATIONS

ELEMENT WITH FIFOs

Descriptions

Features

The GM16C550 is an asynchronous communi-

cations element (ACE) that is functionally

equivalent to the GM16C450, and addition-ally

incorporates a 16byte FIFOs are available on both

the transmitter and receiver, and can be activated by

placing the device in the FIFO mode. After a reset,

the registers of the GM16C550 are identical to those

of the GM16C450.

Fully compatible with GM16C450.

Modem controm signals include

CTS RTS

DSR , DTR , RI and -DCD .

Programmable serial characteristics:

—5-, 6-, 7- or 8-bit characters

— Even-, odd-, or no-parity bit generation and

detection

—1-, 11/2- or 2-stop bit generation

The UART performs serial-to-parallel conver- sion

on data characters received from a peri-pheral

— Baud rate generation (DC to 256K baud)

16 byte FIFO reduces CPU interrupts.

Independent control of transmit, receive, line

status, data set interrupts, FIFOs.

device or

a MODEM, and parallel-to- serial

conversion on data characters received from the

CPU. The CPU can read the com- plete status of l Full status reporting capabilities

the UART at any time during

operation. Status information reported includes the

the functional

Three-state, TTL drive capabilities for bi-

derectional data bus and control bus.

40DIP/44PLCC

type and condition of

being performed by

the transfer operations

the UART, as well as any

error conditions (parity, overrun, framing, or break

interrupt).

Pin Configulation

VCC

DCD

DSR

RCLK

SIN

N.C.

OUT1

DTR

CTS

OUT1

RTS

OUT2

N.C.

INTRPT

DTR

RCLK

RTS

SOUT

CS0

CS1

SIN

SOUT

CS0

RXRDY

OUT2

INTRPT

CS2

BAUDQUT

RXRDY

CS1

CS2

BAUDQUT

XTAL1

ADS

TXRDY

XTAL2

DDIS

DOSTR

DISTR

VSS

DISTR

12 3 4 5 6 7...22

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