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CS91 PDF预览

CS91

更新时间: 2024-02-05 21:20:20
品牌 Logo 应用领域
富士通 - FUJITSU 电容器
页数 文件大小 规格书
9页 102K
描述
Standard cell array

CS91 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8532.24.0060风险等级:5.76
Is Samacsys:N其他特性:RATED AC VOLTAGE (V): 125-400
电容器类型:CERAMIC CAPACITOR介电材料:CERAMIC
JESD-609代码:e3安装特点:THROUGH HOLE MOUNT
多层:No端子数量:2
最高工作温度:85 °C最低工作温度:-25 °C
封装形状:DISK PACKAGE表面贴装:NO
端子面层:TIN OVER NICKEL端子形状:WIRE
Base Number Matches:1

CS91 数据手册

 浏览型号CS91的Datasheet PDF文件第2页浏览型号CS91的Datasheet PDF文件第3页浏览型号CS91的Datasheet PDF文件第4页浏览型号CS91的Datasheet PDF文件第5页浏览型号CS91的Datasheet PDF文件第6页浏览型号CS91的Datasheet PDF文件第7页 
FUJITSU SEMICONDUCTOR  
DATA SHEET  
DS06-20208-3E  
Semicustom  
CMOS  
Standard cell array  
CS91 Series  
DESCRIPTION  
The CS91 series 0.11 µm CMOS standard cell is a line of highly integrated CMOS ASICs featuring high speed  
and low power consumption. This series incorporates up to 48 million gates which have a gate delay time of 16  
ps, resulting in both integration and speed about three times higher than conventional products.  
FEATURES  
• Technology  
: 0.11 µm silicon-gate CMOS, 5- to 8-layer wiring (Copper is used as wire material.) ,  
Low-K (2.7) Inter-layer material (Inter-layer material that has low permittivity)  
• Support for high speed, high integration, low leak internal cell set. Capable of incorporating on the same chip.  
• Supply voltage : +1.2 V 0.1 V (standard specification)  
• Junction temperature range : 40 °C to +125 °C  
• Gate delay time : tpd = 16 ps (1.2 V, inverter, F/O = 1)  
• Gate power consumption : Pd = 6.6 nW/MHz/BC (1.2 V, inverter, F/O = 1)  
• Support for ultra high speed (622 Mbps to 780 Mbps, 2.5 Gbps to 3.125 Gbps, 10 Gbps) interface macros for  
transmission  
• Special interfaces* : P-CML, LVDS, PCI, SSTL, HSTL, T-LVTTL, and others.  
• Buffer cell dedicated to crystal oscillator  
• IP macros*  
: CPU (ARM9, ARM7TDMI) , DSP, PCI, IEEE1394, USB, IrDA, PLL, ADC, DAC, and others.  
• Compiled cells (RAM/ROM/multiplier, and others.)  
• Uses industry standard tools and supports the optimum tools for the application  
• Short-term development using a physical prototyping tool  
• Hierarchical design environment for supporting large-scale circuits  
• Support for SIGNAL INTEGRITY, EMI noise reduction  
• Support for High resolution RC extraction base delay calculation environment  
• Support for optimization environment of power supply wire  
(Continued)  
Copyright©2002-2006 FUJITSU LIMITED All rights reserved  

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