Datasheet > CS401

CS401

更新时间： 2024-02-23 02:07:26

品牌	Logo	应用领域
富士通 - FUJITSU		/
页数	文件大小	规格书
8页	56K
描述
Standard Cell CS401 Series

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CS401 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.65
Base Number Matches：	1

CS401 数据手册

FUJITSU SEMICONDUCTOR

DATA SHEET

DS601-00001-2v0-E

Semicustom

CMOS

Standard Cell

CS401 Series

■ DESCRIPTION

The CS401 series of 28 nm standard cells is a line of CMOS ASICs that satisfy demands for lower power

consumption, higher speed and higher integration.

These cells offer the minimum level of leakage current in the semiconductor industry, and are able to imple-

ment a mixture of core transistors with four different threshold voltages, as appropriate for the applications

ranging from handheld terminals to digital audiovisual equipment.

The integration level in this series is twice the CS302 series with lower power consumption and higher speed.

■ FEATURES

• Technology

: 28 nm Metal-gate CMOS

: Maximum 11-metal layers. Ultra low permittivity material is used for dielectric

inter-layers.

: Four different types of core transistors (low leak, standard, high speed and ultra high

speed) can be used on the same chip.

• Supply voltage : Internal power supply : + 1.0 V 0.1 V

: External power supply : + 1.8 V 0.15 V

(1.8V interface on dual-power supply system)

+ 2.5 V 0.2 V

(2.5V interface on dual-power supply system)

+ 3.3 V 0.3 V

(3.3V interface on dual-power supply system)

• Junction temperature range: − 40 °C to + 125 °C (standard specification)

• Gate power consumption: 0.61 nW / gate (operating condition: 1.0 V, operating rate 0.5, 1 MHz)

• Support high-quality, various types of cell sets developed by FUJITSU SEMICONDUCTOR (from low power

versions to high speed versions).

• Support SRAMs with standby-mode and power-down mode for lower power consumption memories.

• Compiled cells (RAM, ROM, others)

• Support special interfaces (LVDS, SSTL, others).

• Support boundary SCAN test.

• Support use of industry standard libraries.

• Support use of industry standard tools.

• Short-term development using a physical prototyping tool

• One pass design using a physical synthesis tool

• Hierarchical design environment for supporting large-scale circuits

• Support Signal Integrity, EMI noise reduction.

(Continued)

2012.10

12 3 4 5 6 7 8

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