Datasheet > CS201

CS201

更新时间： 2024-01-03 17:25:51

品牌	Logo	应用领域
富士通 - FUJITSU		光电输出元件
页数	文件大小	规格书
9页	70K
描述
Semicustom CMOS Standard Cell

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数据手册

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CS201 技术参数

生命周期：	Active	Reach Compliance Code：	compliant
HTS代码：	8541.40.80.00	风险等级：	5.56
光电设备类型：	TRANSISTOR OUTPUT OPTOCOUPLER

CS201 数据手册

FUJITSU SEMICONDUCTOR

DATA SHEET

DS06-20211-1E

Semicustom

CMOS

Standard Cell

CS201 Series

■ DESCRIPTION

The CS201 series of 65 nm standard cells is a line of CMOS ASICs that satisfy demands for lower power

consumption and higher integration. These cells offer the minimum level of leakage current in the semiconductor

industry, and are able to implement a mixture of core transistors with three different threshold voltages, as

appropriate for the applications ranging from handheld terminals to digital audiovisual equipment.

The integration level in this series is twice the previous series with lower power consumption.

■ FEATURES

• Technology

: 65 nm Si gate CMOS

: 6 to 12 layers of metal wiring.

Ultra Low-K (low permittivity) material is used for dielectric inter-layers.

Three different types of core transistors (low leak, standard and high speed) can be

used on the same chip.

• Power supply voltage : Supports a wide range from + 0.9 V to + 1.3 V

• Operation junction temperature : − 40 °C to + 125 °C (standard)

• Gate delay time

: 11 ps (1.2 V, Inverter, F/O = 1)

• Gate power consumption : 1.77 nW/gate (operating condition: 1.2 V, operating rate 0.5, 1 MHz)

• Reduced chip size achieved by creating the wire bonding pads within the I/O macro regions.

• Support various cell sets (from low power versions to high speed versions)

• Compiled cell (RAM, ROM, others)

• Support large capacity memory “1T-SRAM-Q^®”*¹

“1T-SRAM-Q^®” is the embedded memory which enable maximum 128Mbit.

• Support low-consumption technology “ CoolAdjust^TM”*²

• Support ultra high speed (up to 10 Gbps) interface macros

• Special interfaces (LVDS, SSTL, others)

• Short-term development using a physical prototyping tool

• One pass design using a physical synthesis tool

• Hierarchical design environment for supporting large-scale circuits

• Support Signal Integrity, EMI noise reduction

• Support static timing sign-off

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