Datasheet > CS200L

CS200L

更新时间： 2024-01-04 04:39:06

品牌	Logo	应用领域
富士通 - FUJITSU		/
页数	文件大小	规格书
2页	505K
描述
65nm CMOS Standard Cell

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技术参数
数据手册

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CS200L 技术参数

生命周期：	Contact Manufacturer	Reach Compliance Code：	unknown
风险等级：	5.66	Base Number Matches：	1

CS200L 数据手册

65nm CMOS Standard Cell

CS200 ASIC Series

Server/

Network

HS-Tr

D-

Low Power

LLiinneeuupp

STDD--Tr

STD-Tr

CS200LL

CS200A

UHS-Tr

HV-Tr

D-

HV-Tr

HS-Tr

High End Server

High

High Performance

Performance

Lineup CS200HP

Mobile

Computing

STD-Tr

Lineup CS200

Digital Consumer

LL-Tr

UHS: Ultra High Speed, HS: High Speed

STD: Standard, LL: Low Leakage

Cellular Phone

Fast

Speed

Features

• High integration

• Application specific IPs

– Transistor of 30–50nm gate length (ITRS road map 65nm)

– 12-layer fine pitch, copper wiring, and low-K insulating

material techniques

– Maximum 180 million gates, nearly twice that of 90nm

technology

– Computational cores: ARM7, 9, 11, Communication and

Digital-AV DSP

– Mixed signals: Wide range of ADCs and DACs

– HSIF logics: PCI-Express, XAUI, SATA, DDR, USB, HDMI

• High-speed interface SerDes macros (~10Gbps data rate)

• Wide range of PLLs: standard to high-speed 1.6GHz

• Standard I/Os: LVTTL, SSTL, HSTL, LVDS, P-CML

• Wide supply voltage (0.80V to 1.30V for core)

• Triple Vth Transistor options

• Various packages available (QFP, FBGA, EBGA, PBGA,

FC-BGA)

• Design methodology and support

– 50% reduction in SRAM cell size

– 30% increase in performance over 90nm

• Low power consumption/low leakage current

• I/O with pad structure with fine pad pitch technology for chip

size reduction

• High-speed library and low-power library available

– High speed: CS200HP

– Low leak: CS200L

– Methodology in place to support multi-million-gates

hierarchical designs

– Excellent design center support at Sunnyvale and Dallas

– Worldwide service organizations for global support

• Higher performance, gate propagation delay tpd = 4.4ps

(@1.2V, inverter, and F/O = 1, CS200HP)

• Compiled memory macros: 1T and 6T SRAMs, and ROM

Description

CS200 Series, 65nm standard cells CMOS process technology,

addresses the design challenges of the PDA and mobile computing

market in low power and multi-functionality. It also addresses

the need of ultra high performance design in leading-edge

networking, server computing, and in complex telecom

equipment applications. 65nm technology is available in 300mm

fabrication and supports high volume wafer capacity in multiple

manufacturing locations.

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