Datasheet > CS101

CS101

更新时间： 2024-01-09 07:49:05

品牌	Logo	应用领域
富士通 - FUJITSU		电池
页数	文件大小	规格书
8页	103K
描述
Standard Cell

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技术参数
数据手册

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CS101 技术参数

生命周期：	Contact Manufacturer	Reach Compliance Code：	compliant
ECCN代码：	EAR99	风险等级：	5.69
应用：	POWER	ET产品最小值：	20 V-us
高度：	5.84 mm	长度：	6.6 mm
负载电阻：	0.85 Ω	安装特点：	SURFACE MOUNT
初级绕组数量：	1	次级绕组数量：	1
最高工作温度：	125 °C	最低工作温度：	-55 °C
输出电流 1：	5 A	物理尺寸：	6.6mm x 6.6mm x 5.84mm
初级电感：	2800 µH	子类别：	Other Transformers
表面贴装：	YES	变压器类型：	CURRENT SENSE TRANSFORMER
匝数比 (Np:Ns)：	1:50	宽度：	6.6 mm
Base Number Matches：	1

CS101 数据手册

FUJITSU SEMICONDUCTOR

DATA SHEET

DS06-20210-2E

Semicustom

CMOS

Standard Cell

CS101 Series

■ DESCRIPTION

CS101 series, a 90 nm standard cell product, is a CMOS ASIC that satisfies user’s demands for lower power

consumption and higher speed. The leakage current of the transistors is the minimum level in the industry. Three

types of core transistors with a different threshold voltage can be mixed according to user application.

The design rules match industry standards, and a wide range of IP macros are available for use.

As well as providing a maximum of 100 million gates, approximately twice the level of integration achieved in

previous products, the power consumption per gate is also reduced by about half to 2.7 nW. Also, using the high-

speed library increases the speed by a factor of approximately 1.3, with a gate delay time of 12 ps.

■ FEATURES

• Technology

: 90 nm Si gate CMOS

7- to 10-metal layers.

Low-K (low permittivity) material is used for all dielectric inter-layers.

Three different types of core transistors (low leak, standard, and high speed)

can be used on the same chip.

The design rules comply with industry standard processes.

• Power supply voltage

: +1.2 V 0.1 V (standard)

• Operation junction temperature : − 40 °C to + 125 °C (standard)

• Gate delay time

• Gate power consumption

• High level of integration

: tpd = 12 ps (1.2 V, Inverter, F/O = 1)

: Pd = 2.7 nW/MHz/BC (1.2 V, 2 NAND, F/O = 1)

: Up to 91 million gates

• Reduced chip sized realized by I/O with pad.

• Support for a wide range of cell sets (from low power versions to ultra high speed versions).

• Compliance with industry standard design rules enables non-Fujitsu commercial macros to be easily incorpo-

rated.

• Compiled cell (RAM, ROM, others)

• Support for ultra high speed (up to 10 Gbps) interface macros.

• Special interfaces (LVDS, SSTL2, etc.)

• Supports use of industry standard libraries (.LIB).

• Uses industry standard tools and supports the optimum tools for the application.

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