Datasheet > CE77

CE77

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
富士通 - FUJITSU		/
页数	文件大小	规格书
24页	161K
描述
Semicustom CMOS Embedded array

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CE77 数据手册

FUJITSU SEMICONDUCTOR

DATA SHEET

DS06-20112-2E

Semicustom

CMOS

Embedded array

CE77 Series

■ DESCRIPTION

The CE77 series 0.25 µm CMOS embedded array is a line of highly integrated CMOS ASICs featuring high speed

and low power consumption at the same time.

CE77 series is available in 15 frames with the enhanced lineup of 470 K to 6980 K gates.

■ FEATURES

• Technology

• Supply voltage

: 0.25 µm silicon-gate CMOS, 3- to 4-layer wiring

: +2.5 V 0.2 V (normal) to +1.5 V 0.1 V

• Junction temperature range : −40 °C to +125 °C

• Gate delay time : t^pd= 33 ps (2.5 V, inverter cell High Speed type, F/O = 1, No load)

• Gate power consumption : 0.02 µW/MHz (1.5 V, F/O = 1, No load)

• High-load driving capability : IOL = 2 mA/4 mA/8 mA/12 mA mixable

• Output buffer cells with noise reduction circuits

• Inputs with on-chip input pull-up/pull-down resistors (25 kΩ typical) and bidirectional buffer cells

• Buffer cells dedicated to crystal oscillator

• Special interface (P-CML, LVDS, T-LVTTL, SSTL, PCI, USB, GTL+, and others including those under

development)

• IP macros (CPU, PCI, USB, IrDA, PLL, DAC, ADC, and others including those under development)

• Capable of incorporating compiled cells (RAM/ROM/FIFO/Delay line, and others.)

• Configurable internal bus circuits

• Advanced hardware/software co-design environment

• Support for static timing sign-off

Dramatically reducing the time for generating test vectors for timing verification and the simulation time

• Hierarchical design environment for supporting large-scale circuits

• Simulation (before layout) considering the input slew rate and detailed RC delay calculation (after layout) ,

supporting development with minimized timing trouble after trial manufacture

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