Datasheet > 54HC138

54HC138

更新时间： 2022-09-21 23:47:53

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		/
页数	文件大小	规格书
7页	168K
描述
3-to-8 Line Decoder

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数据手册

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54HC138 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC74VHC138 is an advanced high speed CMOS 3–to–8 decoder

fabricated with silicon gate CMOS technology. It achieves high speed

operation similar to equivalent Bipolar Schottky TTL while maintaining

CMOS low power dissipation.

When the device is enabled, three Binary Select inputs (A0 – A2)

determine which one of the outputs (Y0 – Y7) will go Low. When enable input

E3 is held Low or either E2 or E1 is held High, decoding function is inhibited

and all outputs go high. E3, E2, and E1 inputs are provided to ease cascade

connection and for use as an address decoder for memory systems.

The internal circuit is composed of three stages, including a buffer output

which provides high noise immunity and stable output. The inputs tolerate

voltages up to 7V, allowing the interface of 5V systems to 3V systems.

D SUFFIX

16–LEAD SOIC PACKAGE

CASE 751B–05

DT SUFFIX

16–LEAD TSSOP PACKAGE

CASE 948F–01

•

High Speed: t

= 5.7ns (Typ) at V

= 5V

Low Power Dissipation: I

= 4µA (Max) at T = 25°C

High Noise Immunity: V

Power Down Protection Provided on Inputs

Balanced Propagation Delays

Designed for 2V to 5.5V Operating Range

= V

= 28% V

NIH

NIL CC

Low Noise: V

= 0.8 V (Max)

M SUFFIX

16–LEAD SOIC EIAJ PACKAGE

CASE 966–01

OLP

Pin and Function Compatible with Other Standard Logic Families

Latchup Performance Exceeds 300mA

ESD Performance: HBM > 2000V; Machine Model > 200V

Chip Complexity: 122 FETs or 30.5 Equivalent Gates

ORDERING INFORMATION

MC74VHCXXXD

MC74VHCXXXDT

MC74VHCXXXM

SOIC

TSSOP

SOIC EIAJ

FUNCTION TABLE

Inputs

Outputs

E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

PIN ASSIGNMENT

H = high level (steady state); L = low level (steady state);

X = don’t care

GND

SELECT

INPUTS

ACTIVE–LOW

OUTPUTS

ENABLE

INPUTS

LOGIC DIAGRAM

6/97

REV 1

Motorola, Inc. 1997

12 3 4 5 6 7

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