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CD4046BC PDF预览

CD4046BC

更新时间: 2024-02-17 20:39:06
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
14页 175K
描述
Micropower Phase-Locked Loop

CD4046BC 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP-16针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.23Is Samacsys:N
模拟集成电路 - 其他类型:PHASE LOCKED LOOPJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:5 mm
湿度敏感等级:1功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:5/15 V
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:PLL or Frequency Synthesis Circuits最大供电电压 (Vsup):18 V
最小供电电压 (Vsup):5 V标称供电电压 (Vsup):10 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

CD4046BC 数据手册

 浏览型号CD4046BC的Datasheet PDF文件第2页浏览型号CD4046BC的Datasheet PDF文件第3页浏览型号CD4046BC的Datasheet PDF文件第4页浏览型号CD4046BC的Datasheet PDF文件第5页浏览型号CD4046BC的Datasheet PDF文件第6页浏览型号CD4046BC的Datasheet PDF文件第7页 
October 1987  
Revised January 1999  
CD4046BC  
Micropower Phase-Locked Loop  
The INHIBIT input, when high, disables the VCO and  
source follower to minimize standby power consumption.  
The zener diode is provided for power supply regulation, if  
necessary.  
General Description  
The CD4046BC micropower phase-locked loop (PLL) con-  
sists of a low power, linear, voltage-controlled oscillator  
(VCO), a source follower, a zener diode, and two phase  
comparators. The two phase comparators have a common  
signal input and a common comparator input. The signal  
input can be directly coupled for a large voltage signal, or  
capacitively coupled to the self-biasing amplifier at the sig-  
nal input for a small voltage signal.  
Features  
Wide supply voltage range: 3.0V to 18V  
Low dynamic power consumption: 70 µW (typ.) at fo  
10 kHz, VDD = 5V  
=
Phase comparator I, an exclusive OR gate, provides a digi-  
tal error signal (phase comp. I Out) and maintains 90°  
phase shifts at the VCO center frequency. Between signal  
input and comparator input (both at 50% duty cycle), it may  
lock onto the signal input frequencies that are close to har-  
monics of the VCO center frequency.  
VCO frequency: 1.3 MHz (typ.) at VDD = 10V  
Low frequency drift: 0.06%/°C at VDD = 10V with tem-  
perature  
High VCO linearity: 1% (typ.)  
Phase comparator II is an edge-controlled digital memory  
network. It provides a digital error signal (phase comp. II  
Out) and lock-in signal (phase pulses) to indicate a locked  
condition and maintains a 0° phase shift between signal  
input and comparator input.  
Applications  
FM demodulator and modulator  
Frequency synthesis and multiplication  
Frequency discrimination  
Data synchronization and conditioning  
Voltage-to-frequency conversion  
Tone decoding  
The linear voltage-controlled oscillator (VCO) produces an  
output signal (VCO Out) whose frequency is determined by  
the voltage at the VCOIN input, and the capacitor and resis-  
tors connected to pin C1A, C1B, R1 and R2.  
FSK modulation  
The source follower output of the VCOIN (demodulator Out)  
Motor speed control  
is used with an external resistor of 10 kor more.  
Ordering Code:  
Order Number Package Number  
Package Description  
CD4046BCM  
M16A  
16-Lead Small Outline integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
CD4046BCN  
N16E  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Assignments for SOIC and DIP  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005968.prf  
www.fairchildsemi.com  

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