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74VHC4046MX_NL

更新时间: 2024-02-15 18:21:12
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
16页 223K
描述
Phase Locked Loop, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16

74VHC4046MX_NL 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.7其他特性:CONTAINS THREE PHASE COMPARATORS
模拟集成电路 - 其他类型:PHASE LOCKED LOOPJESD-30 代码:R-PDIP-T16
JESD-609代码:e3长度:19.305 mm
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT APPLICABLE
电源:2/6 V认证状态:Not Qualified
座面最大高度:5.08 mm子类别:PLL or Frequency Synthesis Circuits
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT APPLICABLE宽度:7.62 mm
Base Number Matches:1

74VHC4046MX_NL 数据手册

 浏览型号74VHC4046MX_NL的Datasheet PDF文件第2页浏览型号74VHC4046MX_NL的Datasheet PDF文件第3页浏览型号74VHC4046MX_NL的Datasheet PDF文件第4页浏览型号74VHC4046MX_NL的Datasheet PDF文件第5页浏览型号74VHC4046MX_NL的Datasheet PDF文件第6页浏览型号74VHC4046MX_NL的Datasheet PDF文件第7页 
April 1994  
Revised April 1999  
74VHC4046  
CMOS Phase Lock Loop  
ing the loop out of lock, but is less likely to lock onto har-  
monics than the other two comparators.  
General Description  
The VHC4046 is a low power phase lock loop utilizing  
advanced silicon-gate CMOS technology to obtain high fre-  
quency operation both in the phase comparator and VCO  
sections. This device contains a low power linear voltage  
controlled oscillator (VCO), a source follower, and three  
phase comparators. The three phase comparators have a  
common signal input and a common comparator input. The  
signal input has a self biasing amplifier allowing signals to  
be either capacitively coupled to the phase comparators  
with a small signal or directly coupled with standard input  
logic levels. This device is similar to the CD4046 except  
that the Zener diode of the metal gate CMOS device has  
been replaced with a third phase comparator.  
In a typical application any one of the three comparators  
feed an external filter network which in turn feeds the VCO  
input. This input is a very high impedance CMOS input  
which also drives the source follower. The VCO’s operating  
frequency is set by three external components connected  
to the C1A, C1B, R1 and R2 pins. An inhibit pin is provided  
to disable the VCO and the source follower, providing a  
method of putting the IC in a low power state.  
The source follower is a MOS transistor whose gate is con-  
nected to the VCO input and whose drain connects the  
Demodulator output. This output normally is used by tying  
a resistor from pin 10 to ground, and provides a means of  
looking at the VCO input without loading down modifying  
the characteristics of the PLL filter.  
Phase Comparator I is an exclusive OR (XOR) gate. It pro-  
vides a digital error signal that maintains a 90 phase shift  
between the VCO’s center frequency and the input signal  
(50% duty cycle input waveforms). This phase detector is  
more susceptible to locking onto harmonics of the input fre-  
quency than phase comparator I, but provides better noise  
rejection.  
Features  
Low dynamic power consumption: (VCC = 4.5V)  
Maximum VCO operating frequency: 12 MHz  
(VCC = 4.5V)  
Phase comparator III is an SR flip-flop gate. It can be used  
to provide the phase comparator functions and is similar to  
the first comparator in performance.  
Fast comparator response time (VCC = 4.5V)  
Comparator I:  
25 ns  
Phase comparator II is an edge sensitive digital sequential  
network. Two signal outputs are provided, a comparator  
output and a phase pulse output. The comparator output is  
a 3-STATE output that provides a signal that locks the VCO  
output signal to the input signal with 0 phase shift between  
them. This comparator is more susceptible to noise throw-  
Comparator II: 30 ns  
Comparator III: 25 ns  
VCO has high linearity and high temperature stability  
Pin and function compatible with the 74HC4046  
Ordering Code:  
Order Number Package Number  
Package Description  
74VHC4046M  
74VHC4046MTC  
74VHC4046N  
M16A  
MTC16  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 1999 Fairchild Semiconductor Corporation  
DS011675.prf  
www.fairchildsemi.com  

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