5秒后页面跳转
74VHC161284MTDX_NL PDF预览

74VHC161284MTDX_NL

更新时间: 2024-01-02 15:03:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
11页 115K
描述
Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 6.10 MM, MO-153, TSSOP-48

74VHC161284MTDX_NL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP,
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.19差分输出:NO
驱动器位数:14输入特性:SCHMITT TRIGGER
接口集成电路类型:LINE TRANSCEIVER接口标准:IEEE 1284
JESD-30 代码:R-PDSO-G48JESD-609代码:e3
长度:12.5 mm湿度敏感等级:2
功能数量:13端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
最大接收延迟:30 ns接收器位数:13
座面最大高度:1.2 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
最大传输延迟:30 ns宽度:6.1 mm
Base Number Matches:1

74VHC161284MTDX_NL 数据手册

 浏览型号74VHC161284MTDX_NL的Datasheet PDF文件第2页浏览型号74VHC161284MTDX_NL的Datasheet PDF文件第3页浏览型号74VHC161284MTDX_NL的Datasheet PDF文件第4页浏览型号74VHC161284MTDX_NL的Datasheet PDF文件第5页浏览型号74VHC161284MTDX_NL的Datasheet PDF文件第6页浏览型号74VHC161284MTDX_NL的Datasheet PDF文件第7页 
February 1998  
Revised July 2000  
74VHC161284  
IEEE 1284 Transceiver  
General Description  
Features  
Supports IEEE 1284 Level 1 and Level 2 signaling  
standards for bidirectional parallel communications  
between personal computers and printing peripherals  
The VHC161284 contains eight bidirectional data buffers  
and eleven control/status buffers to implement  
a full  
IEEE 1284 compliant interface. The device supports the  
IEEE 1284 standard and is intended to be used in  
Extended Capabilities Port mode (ECP). The pinout allows  
for easy connection from the Peripheral (A-side) to the  
Host (cable side).  
Replaces the function of two (2) 74ACT1284 devices  
All inputs have hysteresis to provide noise margin  
B and Y output resistance optimized to drive external  
cable  
Outputs on the cable side can be configured to be either  
open drain or high drive (± 14 mA). The pull-up and pull-  
down series termination resistance of these outputs on the  
cable side is optimized to drive an external cable. In addi-  
tion, all inputs (except HLH) and outputs on the cable side  
contain internal pull-up resistors connected to the VCC sup-  
B and Y outputs in high impedance mode during power  
down  
Inputs and outputs on cable side have internal pull-up  
resistors  
Flow-through pin configuration allows easy interface  
ply to provide proper termination and pull-ups for open  
drain mode.  
between the Peripheral and Host  
Outputs on the Peripheral side are standard LOW-drive  
CMOS outputs. The DIR input controls data flow on the  
A1–A8/B1–B8 transceiver pins.  
Ordering Code:  
Ordering Number Package Number  
Package Description  
74VHC161284MEA  
74VHC161284MTD  
MS48A  
MTD48  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Logic Symbol  
Connection Diagram  
© 2000 Fairchild Semiconductor Corporation  
DS500098  
www.fairchildsemi.com  

与74VHC161284MTDX_NL相关器件

型号 品牌 描述 获取价格 数据表
74VHC161FT TOSHIBA 4-bit Binary Counter, TSSOP16B

获取价格

74VHC161M FAIRCHILD 4-Bit Binary Counter with Asynchronous Clear

获取价格

74VHC161MSCX FAIRCHILD 暂无描述

获取价格

74VHC161MTC FAIRCHILD 4-Bit Binary Counter with Asynchronous Clear

获取价格

74VHC161MTCX FAIRCHILD COUNTER|UP|4-BIT BINARY|HC-CMOS|TSSOP|16PIN|PLASTIC

获取价格

74VHC161MTCX_NL FAIRCHILD 暂无描述

获取价格