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74LVXZ161284BTX PDF预览

74LVXZ161284BTX

更新时间: 2024-01-25 01:43:05
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
11页 306K
描述
Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, PDSO48, 6.10 MM, MO-153, TSSOP-48

74LVXZ161284BTX 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:6.10 MM, MO-153, TSSOP-48
针数:48Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.42Is Samacsys:N
差分输出:NO驱动器位数:14
输入特性:SCHMITT TRIGGER接口集成电路类型:LINE TRANSCEIVER
接口标准:IEEE 1284JESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:12.5 mm
功能数量:13端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
最大接收延迟:44 ns接收器位数:13
座面最大高度:1.2 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
电源电压1-最大:5.5 V电源电压1-分钟:3 V
电源电压1-Nom:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
最大传输延迟:44 ns宽度:6.1 mm
Base Number Matches:1

74LVXZ161284BTX 数据手册

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May 2002  
Revised May 2002  
74LVXZ161284  
Low Voltage IEEE 161284 Translating Transceiver  
with Power-Up Protection  
General Description  
The LVXZ161284 contains eight bidirectional data buffers  
Features  
I Supports IEEE 1284 Level 1 and Level 2 signaling  
standards for bidirectional parallel communications  
between personal computers and printing peripherals  
and eleven control/status buffers to implement  
a full  
IEEE 1284 compliant interface. The device supports the  
IEEE 1284 standard and is intended to be used in an  
Extended Capabilities Port mode (ECP). The pinout allows  
for easy connection from the Peripheral (A-side) to the  
Host (cable side).  
I Translation capability allows outputs on the cable side to  
interface with 5V signals  
I All inputs have hysteresis to provide noise margin  
I B and Y output resistance optimized to drive external  
cable  
Outputs on the cable side can be configured to be either  
open drain or high drive ( 14 mA) and are connected to a  
separate power supply pin (VCC-Cable) that allows these  
I B and Y outputs in high impedance mode during power  
down  
outputs to be driven by a higher supply voltage than  
the A-side. The pull-up and pull-down series termination  
resistance of these outputs on the cable side is optimized  
to drive an external cable. In addition, the C inputs and the  
B and Y outputs on the cable side contain internal pull-up  
resistors connected to the VCC-Cable supply to provide  
I C inputs and B, Y outputs on cable side have internal 1.4  
kpull-up resistors  
I Flow-through pin configuration allows easy interface  
between the “Peripheral and Host”  
I Replaces the function of two (2) 74ACT1284 devices  
proper input termination and pull-ups for open drain output  
mode.  
I Power-up protection prevents errors when the printer is  
powered on but no valid signal is at the input pins  
(A9 - A13).  
Outputs on the Peripheral side are standard low-drive  
CMOS outputs designed to interface with 3V logic. The DIR  
input controls data flow on the A1–A8/B1–B8 transceiver  
pins.  
This device also has an added power-up protection feature  
which forces the Y outputs (Y9 - Y13) to a high state after  
power-on until one of the associated inputs (A9 - A13) goes  
HIGH. When an associated input (A9 - A13) goes HIGH, all  
Y outputs (Y9 - Y13) are activated.  
Ordering Code  
Package  
Order Number  
Package Description  
Number  
74LVXZ161284MEA  
74LVXZ161284MEX  
74LVXZ161284MTD  
74LVXZ161284MTX  
MS48A  
MS48A  
MTD48  
MTD48  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
[RAIL]  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
[TAPE and REEL]  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
[RAIL]  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
[TAPE and REEL]  
© 2002 Fairchild Semiconductor Corporation  
DS500729  
www.fairchildsemi.com  

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