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74LVX161284MEA

更新时间： 2024-02-05 03:41:47

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		驱动器接口集成电路光电二极管
页数	文件大小	规格书
11页	116K
描述
Low Voltage IEEE 161284 Translating Transceiver

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74LVX161284MEA 数据手册

January 1999

Revised June 2005

74LVX161284

Low Voltage IEEE 161284 Translating Transceiver

General Description

Features

■ Supports IEEE 1284 Level 1 and Level 2 signaling

standards for bidirectional parallel communications

between personal computers and printing peripherals

The LVX161284 contains eight bidirectional data buffers

and eleven control/status buffers to implement

a full

IEEE 1284 compliant interface. The device supports the

IEEE 1284 standard and is intended to be used in an

Extended Capabilities Port mode (ECP). The pinout allows

for easy connection from the Peripheral (A-side) to the

Host (cable side).

■ Translation capability allows outputs on the cable side to

interface with 5V signals

■ All inputs have hysteresis to provide noise margin

■ B and Y output resistance optimized to drive external

cable

Outputs on the cable side can be configured to be either

open drain or high drive ( 14 mA) and are connected to a

separate power supply pin (V_CC-cable) to allow these out-

■ B and Y outputs in high impedance mode during power

down

puts to be driven by a higher supply voltage than the A-

side. The pull-up and pull-down series termination resis-

tance of these outputs on the cable side is optimized to

drive an external cable. In addition, all inputs (except HLH)

and outputs on the cable side contain internal pull-up resis-

tors connected to the V_CC-cable supply to provide proper

■ Inputs and outputs on cable side have internal pull-up

resistors

■ Flow-through pin configuration allows easy interface

between the “Peripheral and Host”

■ Replaces the function of two (2) 74ACT1284 devices

termination and pull-ups for open drain mode.

Outputs on the Peripheral side are standard low-drive

CMOS outputs designed to interface with 3V logic. The DIR

input controls data flow on the A₁–A₈/B₁–B₈transceiver

pins.

Ordering Code

Order Number

74LVX161284MEA

74LVX161284MTD

Package Number

MS48A

Package Description

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

MTD48

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

Description

High Drive Enable Input (Active HIGH)

Direction Control Input

Inputs or Outputs

DIR

A₁–A₈

B₁–B₈

A₉–A₁₃

Y₉–Y₁₃

Inputs or Outputs

Inputs

Outputs

₁₄–A₁₇

Outputs

C₁₄–C₁₇

PLH_IN

PLH

Inputs

Peripheral Logic HIGH Input

Peripheral Logic HIGH Output

Host Logic HIGH Input

Host Logic HIGH Output

HLH_IN

HLH

DS500202

www.fairchildsemi.com

12 3 4 5 6 7...11

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与74LVX161284MEA相关器件

型号	品牌	描述	获取价格	数据表
74LVX161284MEA_NL	FAIRCHILD	Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 0.300 INCH, LEAD FREE, MO-118	获取价格
74LVX161284MEAX	FAIRCHILD	Low Voltage IEEE 161284 Translating Transceiver	获取价格
74LVX161284MEAX_NL	FAIRCHILD	Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 0.300 INCH, MO-118, SSOP-48	获取价格
74LVX161284MTD	FAIRCHILD	Low Voltage IEEE 161284 Translating Transceiver	获取价格
74LVX161284MTD_NL	FAIRCHILD	Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 6.10 MM, LEAD FREE, MO-153, T	获取价格
74LVX161284MTDX	FAIRCHILD	Low Voltage IEEE 161284 Translating Transceiver	获取价格

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