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74ACT161MTC PDF预览

74ACT161MTC

更新时间: 2024-02-29 04:07:33
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
13页 336K
描述
Synchronous Presettable Binary Counter

74ACT161MTC 技术参数

生命周期:Contact Manufacturer包装说明:TSSOP-16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.61Is Samacsys:N
计数方向:UP系列:ACT
JESD-30 代码:R-PDSO-G16长度:5 mm
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
工作模式:SYNCHRONOUS位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):10.5 ns座面最大高度:1.2 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:4.4 mm最小 fmax:85 MHz
Base Number Matches:1

74ACT161MTC 数据手册

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74ACT161  
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER  
HIGH SPEED:  
MAX = 290MHz (TYP.) at VCC = 5V  
LOW POWER DISSIPATION:  
CC = 8µA(MAX.) at TA=25°C  
COMPATIBLE WITH TTL OUTPUTS  
VIH = 2V (MIN.), VIL = 0.8V (MAX.)  
50TRANSMISSION LINE DRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 24mA (MIN)  
BALANCED PROPAGATION DELAYS:  
tPLH tPHL  
f
I
DIP  
SOP  
TSSOP  
T & R  
ORDER CODES  
PACKAGE  
TUBE  
DIP  
SOP  
74ACT161B  
74ACT161M  
OPERATING VOLTAGE RANGE:  
74ACT161MTR  
74ACT161TTR  
V
CC (OPR) = 4.5V to 5.5V  
TSSOP  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 161  
IMPROVED LATCH-UP IMMUNITY  
counting and allows information on Parallel Data  
inputs to be loaded into the flip-flop on the next  
rising edge of CLOCK. With LOAD and CLEAR  
HIGH, PE and TE permit counting when both are  
HIGH. Conversely, a LOW signal on either PE and  
TE inhibits counting.  
The CARRY OUTPUT is HIGH when TE is HIGH  
and counter is in state 15.  
The device is designed to interface directly High  
Speed CMOS systems with TTL, NMOS and  
CMOS output voltage levels.  
DESCRIPTION  
The 74ACT161 is an advanced high-speed CMOS  
SYNCRONOUS PRESETTABLE COUNTER  
fabricated with sub-micron silicon gate and  
double-layer metal wiring C2MOS tecnology. It is a  
4 bit binary counter with Asynchronous Clear.  
The circuit have four fundamental modes of  
operation, in order of preference: synchronous  
reset, parallel load, count-up and hold. Four  
control inputs, (CLEAR), (LOAD), (PE) and (TE),  
determine the mode of operation as shown in the  
Truth Table. A LOW signal on CLEAR overrides  
counting and parallel loading and sets all outputs  
on LOW state. A LOW signal on LOAD overrides  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/13  

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