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100350QC PDF预览

100350QC

更新时间: 2024-02-12 19:08:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路
页数 文件大小 规格书
7页 77K
描述
Low Power Hex D-Type Latch

100350QC 技术参数

生命周期:Contact Manufacturer包装说明:QCCJ,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.73Is Samacsys:N
其他特性:WITH DUAL LATCH ENABLE系列:100K
JESD-30 代码:S-PQCC-J28长度:11.43 mm
逻辑集成电路类型:D LATCH位数:6
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:
输出特性:OPEN-EMITTER输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
传播延迟(tpd):1.2 ns座面最大高度:4.57 mm
表面贴装:YES技术:ECL
温度等级:OTHER端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
触发器类型:LOW LEVEL宽度:11.43 mm
Base Number Matches:1

100350QC 数据手册

 浏览型号100350QC的Datasheet PDF文件第2页浏览型号100350QC的Datasheet PDF文件第3页浏览型号100350QC的Datasheet PDF文件第4页浏览型号100350QC的Datasheet PDF文件第5页浏览型号100350QC的Datasheet PDF文件第6页浏览型号100350QC的Datasheet PDF文件第7页 
July 1988  
Revised August 2000  
100350  
Low Power Hex D-Type Latch  
General Description  
The 100350 contains six D-type latches with true and com-  
Features  
20% power reduction of the 100150  
plement outputs, a pair of common Enables (Ea and Eb),  
2000V ESD protection  
and a common Master Reset (MR). A Q output follows its D  
input when both Ea and Eb are LOW. When either Ea or Eb  
Pin/function compatible with 100150  
Voltage compensated operating range = −4.2V to 5.7V  
(or both) are HIGH, a latch stores the last valid data  
present on its D input before Ea or Eb went HIGH. The MR  
input overrides all other inputs and makes the Q outputs  
LOW. All inputs have 50 kpull-down resistors.  
Ordering Code:  
Order Number Package Number  
Package Description  
100350PC  
100350QC  
N24E  
V28A  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide  
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square  
Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagrams  
24-Pin DIP  
Pin Descriptions  
28-Pin PLCC  
Pin Names  
Description  
D0D5  
Ea, Eb  
MR  
Data Inputs  
Common Enable Inputs (Active LOW)  
Asynchronous Master Reset Input  
Data Outputs  
Q0Q5  
Q0Q5  
Complementary Data Outputs  
© 2000 Fairchild Semiconductor Corporation  
DS009884  
www.fairchildsemi.com  

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