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XRT86VL30IV PDF预览

XRT86VL30IV

更新时间： 2024-01-12 09:44:58
品牌 Logo 应用领域
艾科嘉 - EXAR 数字传输控制器电信集成电路电信电路
页数 文件大小 规格书
62页 359K
描述
T1/E1/J1 BITS ELEMENT - HARDWARE MANUAL

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XRT86VL30IV 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred零件包装代码：QFP
包装说明：14 X 20 MM, 1.40 MM HEIGHT, GREEN, LQFP-128针数：128
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.07JESD-30 代码：R-PQFP-G128
JESD-609代码：e3长度：20 mm
湿度敏感等级：3功能数量：1
端子数量：128最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.6 mm
标称供电电压：1.8 V表面贴装：YES
电信集成电路类型：FRAMER温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：14 mm
Base Number Matches：1

XRT86VL30IV 数据手册

 浏览型号XRT86VL30IV的Datasheet PDF文件第2页浏览型号XRT86VL30IV的Datasheet PDF文件第3页浏览型号XRT86VL30IV的Datasheet PDF文件第4页浏览型号XRT86VL30IV的Datasheet PDF文件第5页浏览型号XRT86VL30IV的Datasheet PDF文件第6页浏览型号XRT86VL30IV的Datasheet PDF文件第7页 
XRT86VL30  
T1/E1/J1 BITS ELEMENT - HARDWARE MANUAL  
SEPTEMBER 2008  
REV. 1.0.3  
Receive LAPD Message frames from the incoming  
T1/E1/J1 data stream and write the contents into the  
Receive HDLC buffers. The framer also contains a  
Transmit and Overhead Data Input port, which  
permits Data Link Terminal Equipment direct access  
to the outbound T1/E1/J1 frames. Likewise, a  
Receive Overhead output data port permits Data Link  
Terminal Equipment direct access to the Data Link  
bits of the inbound T1/E1/J1 frames.  
GENERAL DESCRIPTION  
The XRT86VL30 is a single channel T1/E1/J1 BITS  
clock recovery element and framer and LIU  
integrated solution featuring R3 technology  
(Relayless, Reconfigurable, Redundancy).  
The  
physical interface is optimized with internal  
impedance, and with the patented pad structure, the  
XRT86VL30 provides protection from power failures  
and hot swapping.  
The XRT86VL30 fully meets all of the latest T1/E1/J1  
specifications: ANSI T1.101-1999, ANSI T1/E1.107-  
1988, ANSI T1/E1.403-1995, ANSI T1/E1.231-1993,  
ANSI T1/E1.408-1990, AT&T TR 62411 (12-90)  
TR54016, and ITU G-703 (Including Section 13 -  
Synchronization), G.704, G706 and G.733, AT&T  
Pub. 43801, and ETS 300 011, 300 233, JT G.703, JT  
G.704, JT G706, I.431. Extensive test and diagnostic  
functions include Loop-backs, Boundary scan,  
Pseudo Random bit sequence (PRBS) test pattern  
generation, Performance Monitor, Bit Error Rate  
(BER) meter, forced error insertion, and LAPD  
unchannelized data payload processing according to  
ITU-T standard Q.921.  
The XRT86VL30 contains an integrated DS1/E1/J1  
framer and LIU which provides DS1/E1/J1 framing  
and error accumulation in accordance with ANSI/  
ITU_T specifications. The framer has its own framing  
synchronizer and transmit-receive slip buffers. The  
slip buffers can be independently enabled or disabled  
as required and can be configured to frame to the  
common DS1/E1/J1 signal formats.  
The Framer block contains its own Transmit and  
Receive T1/E1/J1 Framing function. There are 3  
Transmit HDLC controllers which encapsulate  
contents of the Transmit HDLC buffers into LAPD  
Message frames. There are 3 Receive HDLC  
controllers which extract the payload content of  
APPLICATIONS AND FEATURES (NEXT PAGE)  
FIGURE 1. XRT86VL30 SINGLE CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO  
External Data  
Link Controller  
Local PCM  
Tx Overhead In  
Rx Overhead Out  
Highway  
XRT86VL30  
1:2 Turns Ratio  
1:1 Turns Ratio  
TTIP  
2-Frame  
Slip Buffer  
Elastic Store  
Tx Serial  
Data In  
Tx LIU  
Interface  
Tx Framer  
Rx Framer  
TRING  
Tx Serial  
Clock  
LLB  
LB  
RTIP  
2-Frame  
Slip Buffer  
Elastic Store  
Rx Serial  
Data Out  
Rx LIU  
Interface  
RRING  
Rx Serial  
Clock  
LIU &  
Loopback  
Control  
PRBS  
Generator &  
Analyser  
HDLC/LAPD  
Controllers  
Performance  
Monitor  
RxLOS  
Line Side  
8kHz sync  
OSC  
DMA  
Interface  
Microprocessor  
Interface  
Signaling &  
Alarms  
JTAG  
Back Plane  
1.544-16.384 Mbit/s  
WR  
ALE_AS  
RD  
4
3
µP  
Select  
INT  
System (Terminal) Side  
D[7:0]  
A[11:0]  
RDY_DTACK  
TxON  
Intel/Motorola µP  
Configuration, Control &  
Status Monitor  
Memory  
Exar Corporation 48720 Kato Road, Fremont CA, 94538  
•
(510) 668-7000  
•
FAX (510) 668-7017  
•
www.exar.com  
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