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UPD45128841G5-A80L-9JF PDF预览

UPD45128841G5-A80L-9JF

更新时间: 2024-01-12 15:31:01
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路光电二极管动态存储器时钟
页数 文件大小 规格书
92页 669K
描述
128M-bit Synchronous DRAM 4-bank, LVTTL

UPD45128841G5-A80L-9JF 技术参数

生命周期:Transferred零件包装代码:TSOP2
包装说明:TSOP2,针数:54
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.19
访问模式:FOUR BANK PAGE BURST最长访问时间:6 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-PDSO-G54
长度:22.22 mm内存密度:134217728 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:8
功能数量:1端口数量:1
端子数量:54字数:16777216 words
字数代码:16000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16MX8封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE认证状态:Not Qualified
座面最大高度:1.2 mm自我刷新:YES
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

UPD45128841G5-A80L-9JF 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD45128441, 45128841, 45128163  
128M-bit Synchronous DRAM  
4-bank, LVTTL  
Description  
The µPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access  
memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively.  
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.  
All inputs and outputs are synchronized with the positive edge of the clock.  
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).  
These products are packaged in 54-pin TSOP (II).  
Features  
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge  
Pulsed interface  
Possible to assert random column address in every cycle  
Quad internal banks controlled by BA0(A13) and BA1(A12)  
Byte control (×16) by LDQM and UDQM  
Programmable Wrap sequence (Sequential / Interleave)  
Programmable burst length (1, 2, 4, 8 and full page)  
Programmable /CAS latency (2 and 3)  
Automatic precharge and controlled precharge  
CBR (Auto) refresh and self refresh  
• ×4, ×8, ×16 organization  
Single 3.3 V ± 0.3 V power supply  
LVTTL compatible inputs and outputs  
4,096 refresh cycles / 64 ms  
Burst termination by Burst stop command and Precharge command  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for  
availability and additional information.  
Document No. E0031N30 (Ver. 3.0)  
Date Published August 2001 CP (K)  
Printed in Japan  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.  

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