Datasheet > 存储 > DRAM> EBE11UD8AGFA-4A-E

EBE11UD8AGFA-4A-E

更新时间： 2024-01-17 06:00:57

品牌	Logo	应用领域
尔必达 - ELPIDA		存储内存集成电路动态存储器双倍数据速率时钟
页数	文件大小	规格书
23页	202K
描述
1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)

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EBE11UD8AGFA-4A-E 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	DIMM, DIMM240,40	Reach Compliance Code：	compliant
风险等级：	5.75	最长访问时间：	0.6 ns
最大时钟频率 (fCLK)：	200 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PDMA-N240	内存密度：	8589934592 bit
内存集成电路类型：	DDR DRAM MODULE	内存宽度：	64
端子数量：	240	字数：	134217728 words
字数代码：	128000000	组织：	128MX64
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIMM	封装等效代码：	DIMM240,40
封装形状：	RECTANGULAR	封装形式：	MICROELECTRONIC ASSEMBLY
电源：	1.8 V	认证状态：	Not Qualified
刷新周期：	8192	最大待机电流：	0.128 A
子类别：	DRAMs	最大压摆率：	2.88 mA
标称供电电压 (Vsup)：	1.8 V	表面贴装：	NO
技术：	CMOS	端子形式：	NO LEAD
端子节距：	1 mm	端子位置：	DUAL
Base Number Matches：	1

EBE11UD8AGFA-4A-E 数据手册

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DATA SHEET

1GB Unbuffered DDR2 SDRAM DIMM

EBE11UD8AGFA (128M words × 64 bits, 2 Ranks)

Description

Features

The EBE11UD8AGFA is 128M words × 64 bits, 2 ranks

DDR2 SDRAM unbuffered module, mounting 16 pieces

of 512M bits DDR2 SDRAM sealed in FBGA (µBGA^)

package. Read and write operations are performed at

the cross points of the CK and the /CK. This high-

speed data transfer is realized by the 4 bits prefetch-

pipelined architecture. Data strobe (DQS and /DQS)

both for read and write are available for high speed and

reliable data bus design. By setting extended mode

set enable or disable. This module provides high

density mounting without utilizing surface mount

• 240-pin socket type dual in line memory module

(DIMM)

PCB height: 30.0mm

Lead pitch: 1.0mm

Lead-free (RoHS compliant)

• Power supply: VDD = 1.8V± 0.1V

• Data rate: 667Mbps/533Mbps/400Mbps (max.)

• SSTL_18 compatible I/O

• Double-data-rate architecture: two data transfers per

clock cycle

• Bi-directional, differential data strobe (DQS and

/DQS) is transmitted/received with data, to be used in

capturing data at the receiver

technology.

Decoupling capacitors are mounted

beside each FBGA (µBGA) on the module board.

• DQS is edge aligned with data for READs: center-

aligned with data for WRITEs

Note: Do not push the components or drop the

modules in order to avoid mechanical defects,

which may result in electrical defects.

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge: data

and data mask referenced to both edges of DQS

• Four internal banks for concurrent operation

(components)

• Data mask (DM) for write data

• Burst lengths: 4, 8

• /CAS Latency (CL): 3, 4, 5

• Auto precharge operation for each burst access

• Auto refresh and self refresh modes

• Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• Posted CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• /DQS can be disabled for single-ended Data Strobe

operation

Document No. E0782E20 (Ver. 2.0)

Date Published October 2005 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2005

12 3 4 5 6 7...23

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EBE11UD8AGFA-5C-E	ELPIDA	1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)	获取价格
EBE11UD8AGFA-6E-E	ELPIDA	1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)	获取价格
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EBE11UD8AGSA-5C-E	ELPIDA	1GB DDR2 SDRAM SO-DIMM (128M words x 64 bits, 2 Ranks)	获取价格
EBE11UD8AGSA-6E-E	ELPIDA	1GB DDR2 SDRAM SO-DIMM (128M words x 64 bits, 2 Ranks)	获取价格
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