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EBE10UE8AEFB-8G-F PDF预览

EBE10UE8AEFB-8G-F

更新时间: 2024-02-22 07:30:36
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率
页数 文件大小 规格书
30页 229K
描述
1GB Unbuffered DDR2 SDRAM DIMM

EBE10UE8AEFB-8G-F 技术参数

生命周期:Obsolete零件包装代码:DIMM
包装说明:DIMM,针数:240
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.32风险等级:5.84
访问模式:SINGLE BANK PAGE BURST最长访问时间:0.4 ns
其他特性:AUTO/SELF REFRESH; SEATED HGT-NOM; WD-MAXJESD-30 代码:R-XDMA-N240
长度:133.35 mm内存密度:1073741824 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:8
功能数量:1端口数量:1
端子数量:240字数:134217728 words
字数代码:128000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:128MX8封装主体材料:UNSPECIFIED
封装代码:DIMM封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY认证状态:Not Qualified
座面最大高度:30 mm自我刷新:YES
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:NO
技术:CMOS温度等级:OTHER
端子形式:NO LEAD端子节距:1 mm
端子位置:DUAL宽度:3.18 mm
Base Number Matches:1

EBE10UE8AEFB-8G-F 数据手册

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PRELIMINARY DATA SHEET  
1GB Unbuffered DDR2 SDRAM DIMM  
EBE10UE8AEFB (128M words × 64 bits, 1 Rank)  
Specifications  
Features  
Density: 1GB  
Double-data-rate architecture; two data transfers per  
clock cycle  
Organization  
The high-speed data transfer is realized by the 4 bits  
prefetch pipelined architecture  
128M words × 64 bits, 1 rank  
Mounting 8 pieces of 1G bits DDR2 SDRAM sealed  
in FBGA  
Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
Package: 240-pin socket type dual in line memory  
module (DIMM)  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
PCB height: 30.0mm  
Lead pitch: 1.0mm  
Differential clock inputs (CK and /CK)  
Lead-free (RoHS compliant)  
(EBE10UE8AEFB-xx-E)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Lead-free (RoHS compliant) and Halogen-free  
(EBE10UE8AEFB-xx-F)  
Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
Power supply: VDD = 1.8V ± 0.1V  
Data rate: 800Mbps/667Mbps (max.)  
Data mask (DM) for write data  
Posted /CAS by programmable additive latency for  
better command and data bus efficiency  
Eight internal banks for concurrent operation  
(components)  
Off-Chip-Driver Impedance Adjustment and On-Die-  
Termination for better signal quality  
Interface: SSTL_18  
Burst lengths (BL): 4, 8  
/CAS Latency (CL): 3, 4, 5, 6  
/DQS can be disabled for single-ended Data Strobe  
operation  
Precharge: auto precharge option for each burst  
access  
Refresh: auto-refresh, self-refresh  
Refresh cycles: 8192 cycles/64ms  
Average refresh period  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
Operating case temperature range  
TC = 0°C to +95°C  
Document No. E1402E10 (Ver.1.0)  
Date Published October 2008 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2008  

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