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EBD51RC4AKFA-7B PDF预览

EBD51RC4AKFA-7B

更新时间: 2024-01-18 10:41:58
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率
页数 文件大小 规格书
19页 198K
描述
512MB Registered DDR SDRAM DIMM (64M words X 72 bits, 1 Rank)

EBD51RC4AKFA-7B 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM, DIMM184
针数:184Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.82Is Samacsys:N
访问模式:SINGLE BANK PAGE BURST最长访问时间:0.75 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N184
内存密度:4831838208 bit内存集成电路类型:DDR DRAM MODULE
内存宽度:72功能数量:1
端口数量:1端子数量:184
字数:67108864 words字数代码:64000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64MX72
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM184
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):260电源:2.5 V
认证状态:Not Qualified刷新周期:8192
自我刷新:YES最大待机电流:0.444 A
子类别:Other Memory ICs最大压摆率:5.25 mA
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

EBD51RC4AKFA-7B 数据手册

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DATA SHEET  
512MB Registered DDR SDRAM DIMM  
EBD51RC4AKFA (64M words × 72 bits, 1 Rank)  
Description  
Features  
The EBD51RC4AKFA is a 64M words × 72 bits, 1 rank  
Double Data Rate (DDR) SDRAM Module, mounting 18  
pieces of DDR SDRAM sealed in TSOP package.  
Read and write operations are performed at the cross  
points of the CK and the /CK. This high-speed data  
transfer is realized by the 2-bit prefetch-pipelined  
architecture. Data strobe (DQS) both for read and  
write are available for high speed and reliable data bus  
design. By setting extended mode register, the on-chip  
Delay Locked Loop (DLL) can be set enable or disable.  
This module provides high density mounting without  
184-pin socket type dual in line memory module  
(DIMM)  
PCB height: 30.48mm  
Lead pitch: 1.27mm  
2.5V power supply  
Data rate: 333Mbps/266Mbps (max.)  
2.5 V (SSTL_2 compatible) I/O  
Double Data Rate architecture; two data transfers per  
clock cycle  
Bi-directional, data strobe (DQS) is transmitted  
/received with data, to be used in capturing data at  
the receiver  
utilizing surface mount technology.  
Decoupling  
capacitors are mounted beside each TSOP on the  
module board.  
Data inputs and outputs are synchronized with DQS  
4 internal banks for concurrent operation  
(Component)  
DQS is edge aligned with data for READs; center  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
referenced to both edges of DQS  
Auto precharge option for each burst access  
Programmable burst length: 2, 4, 8  
Programmable /CAS latency (CL): 2, 2.5  
Refresh cycles: (8192 refresh cycles /64ms)  
7.8µs maximum average periodic refresh interval  
2 variations of refresh  
Auto refresh  
Self refresh  
1 piece of PLL clock driver, 2 pieces of register  
drivers and 1 piece of serial EEPROM (2k bits  
EEPROM) for Presence Detect (PD)  
Document No. E0377E20 (Ver. 2.0)  
Date Published January 2004 (K) Japan  
URL: http://www.elpida.com  
Elpida Memory,Inc. 2003-2004  

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