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EBD25UC8AAFA-6B PDF预览

EBD25UC8AAFA-6B

更新时间: 2024-02-13 15:07:06
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率
页数 文件大小 规格书
17页 168K
描述
256MB Unbuffered DDR SDRAM DIMM

EBD25UC8AAFA-6B 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM,
针数:184Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.92Is Samacsys:N
访问模式:SINGLE BANK PAGE BURST最长访问时间:0.7 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-XDMA-N184
内存密度:2147483648 bit内存集成电路类型:DDR DRAM MODULE
内存宽度:64湿度敏感等级:1
功能数量:1端口数量:1
端子数量:184字数:33554432 words
字数代码:32000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32MX64封装主体材料:UNSPECIFIED
封装代码:DIMM封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):225
认证状态:Not Qualified自我刷新:YES
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

EBD25UC8AAFA-6B 数据手册

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PRELIMINARY DATA SHEET  
256MB Unbuffered DDR SDRAM DIMM  
EBD25UC8AAFA-6B (32M words × 64 bits, 1 Rank)  
Description  
Features  
The EBD25UC8AAFA-6B is 32M words × 64 bits, 1  
rank Double Data Rate (DDR) SDRAM unbuffered  
module, mounting 8 pieces of 256M bits DDR SDRAM  
sealed in TSOP package. Read and write operations  
are performed at the cross points of the CK and the  
/CK. This high-speed data transfer is realized by the 2  
bits prefetch-pipelined architecture. Data strobe (DQS)  
both for read and write are available for high speed and  
reliable data bus design. By setting extended mode  
register, the on-chip Delay Locked Loop (DLL) can be  
set enable or disable. This module provides high  
density mounting without utilizing surface mount  
184-pin socket type dual in line memory module  
(DIMM)  
PCB height: 31.75mm  
Lead pitch: 1.27mm  
2.5V power supply  
Data rate: 333Mbps (max.)  
2.5 V (SSTL_2 compatible) I/O  
Double Data Rate architecture; two data transfers per  
clock cycle  
Bi-directional, data strobe (DQS) is transmitted  
/received with data, to be used in capturing data at  
the receiver  
technology.  
Decoupling capacitors are mounted  
beside each TSOP on the module board.  
Data inputs and outputs are synchronized with DQS  
4 internal banks for concurrent operation  
(Component)  
DQS is edge aligned with data for READs; center  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
referenced to both edges of DQS  
Auto precharge option for each burst access  
Programmable burst length: 2, 4, 8  
Programmable /CAS latency (CL): 2, 2.5  
Refresh cycles: (8192 refresh cycles /64ms)  
7.8µs maximum average periodic refresh interval  
2 variations of refresh  
Auto refresh  
Self refresh  
Document No. E0390E10 (Ver. 1.0)  
Date Published June 2003 (K) Japan  
URL: http://www.elpida.com  
This product became EOL in June, 2004.  
Elpida Memory, Inc. 2003  

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