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EBD25EC8AKFA-5B-E PDF预览

EBD25EC8AKFA-5B-E

更新时间: 2024-01-22 21:46:35
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率
页数 文件大小 规格书
19页 179K
描述
DDR DRAM Module, 32MX72, 0.7ns, CMOS, DIMM-184

EBD25EC8AKFA-5B-E 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:DIMM, DIMM184Reach Compliance Code:compliant
风险等级:5.83Is Samacsys:N
最长访问时间:0.7 ns最大时钟频率 (fCLK):200 MHz
I/O 类型:COMMONJESD-30 代码:R-PDMA-N184
内存密度:2415919104 bit内存集成电路类型:DDR DRAM MODULE
内存宽度:72端子数量:184
字数:33554432 words字数代码:32000000
最高工作温度:70 °C最低工作温度:
组织:32MX72输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:DIMM
封装等效代码:DIMM184封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY电源:2.6 V
认证状态:Not Qualified刷新周期:8192
子类别:DRAMs标称供电电压 (Vsup):2.6 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

EBD25EC8AKFA-5B-E 数据手册

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PRELIMINARY DATA SHEET  
256MB Unbuffered DDR SDRAM DIMM  
EBD25EC8AKFA-5 (32M words × 72 bits, 1 Rank)  
Description  
Features  
The EBD25EC8AKFA is 32M words × 72 bits, 1 rank  
Double Data Rate (DDR) SDRAM unbuffered module,  
mounting 9 pieces of 256M bits DDR SDRAM sealed in  
184-pin socket type dual in line memory module  
(DIMM)  
PCB height: 31.75mm  
Lead pitch: 1.27mm  
2.5 V power supply  
Data rate: 400Mbps (max.)  
2.5 V (SSTL_2 compatible) I/O  
TSOP package.  
Read and write operations are  
performed at the cross points of the CK and the /CK.  
This high-speed data transfer is realized by the 2 bits  
prefetch-pipelined architecture. Data strobe (DQS)  
both for read and write are available for high speed and  
reliable data bus design. By setting extended mode  
register, the on-chip Delay Locked Loop (DLL) can be  
set enable or disable. This module provides high  
density mounting without utilizing surface mount  
Double Data Rate architecture; two data transfers per  
clock cycle  
Bi-directional, data strobe (DQS) is transmitted  
/received with data, to be used in capturing data at  
the receiver  
technology.  
Decoupling capacitors are mounted  
beside each TSOP on the module board.  
Data inputs and outputs are synchronized with DQS  
4 internal banks for concurrent operation  
(Component)  
DQS is edge aligned with data for READs; center  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
referenced to both edges of DQS  
Data mask (DM) for write data  
Auto precharge option for each burst access  
Programmable burst length: 2, 4, 8  
Programmable /CAS latency (CL): 3  
Programmable output driver strength: normal/weak  
Refresh cycles: (8192 refresh cycles /64ms)  
7.8µs maximum average periodic refresh interval  
2 variations of refresh  
Auto refresh  
Self refresh  
Document No. E0354E30 (Ver. 3.0)  
Date Published June 2003 (K) Japan  
URL: http://www.elpida.com  
Elpida Memory , Inc. 2003  

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