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EBD11RD8ADFA-7A-E PDF预览

EBD11RD8ADFA-7A-E

更新时间: 2024-01-27 04:39:08
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率
页数 文件大小 规格书
19页 160K
描述
DDR DRAM Module, 128MX72, 0.75ns, CMOS, DIMM-184

EBD11RD8ADFA-7A-E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM,
针数:184Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.84访问模式:DUAL BANK PAGE BURST
最长访问时间:0.75 ns其他特性:AUTO/SELF REFRESH
JESD-30 代码:R-XDMA-N184JESD-609代码:e4
内存密度:9663676416 bit内存集成电路类型:DDR DRAM MODULE
内存宽度:72功能数量:1
端口数量:1端子数量:184
字数:134217728 words字数代码:128000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128MX72
封装主体材料:UNSPECIFIED封装代码:DIMM
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):260认证状态:Not Qualified
自我刷新:YES最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子面层:Gold (Au)
端子形式:NO LEAD端子位置:DUAL
处于峰值回流温度下的最长时间:50Base Number Matches:1

EBD11RD8ADFA-7A-E 数据手册

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PRELIMINARY DATA SHEET  
1GB Registered DDR SDRAM DIMM  
EBD11RD8ADFA (128M words × 72 bits, 2 Ranks)  
Description  
Features  
The EBD11RD8ADFA is a 128M words × 72 bits, 2  
184-pin socket type dual in line memory module  
(DIMM)  
ranks Double Data Rate (DDR) SDRAM Module,  
mounting 18 pieces of DDR SDRAM sealed in TSOP  
package. Read and write operations are performed at  
the cross points of the CK and the /CK. This high-  
speed data transfer is realized by the 2-bit prefetch-  
pipelined architecture. Data strobe (DQS) both for read  
and write are available for high speed and reliable data  
bus design. By setting extended mode register, the on-  
chip Delay Locked Loop (DLL) can be set enable or  
disable. This module provides high density mounting  
without utilizing surface mount technology. Decoupling  
capacitors are mounted beside each TSOP on the  
module board.  
PCB height: 30.48mm  
Lead pitch: 1.27mm  
2.5V power supply  
Data rate: 333Mbps/266Mbps (max.)  
2.5 V (SSTL_2 compatible) I/O  
Double Data Rate architecture; two data transfers per  
clock cycle  
Bi-directional, data strobe (DQS) is transmitted  
/received with data, to be used in capturing data at  
the receiver  
Data inputs and outputs are synchronized with DQS  
4 internal banks for concurrent operation  
(Component)  
DQS is edge aligned with data for READs; center  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
referenced to both edges of DQS  
Data mask (DM) for write data  
Auto precharge option for each burst access  
Programmable burst length: 2, 4, 8  
Programmable /CAS latency (CL): 2, 2.5  
Refresh cycles: (8192 refresh cycles /64ms)  
7.8µs maximum average periodic refresh interval  
2 variations of refresh  
Auto refresh  
Self refresh  
1 piece of PLL clock driver, 2 piece of register driver  
and 1 piece of serial EEPROM (2k bits EEPROM) for  
Presence Detect (PD)  
Document No. E0441E10 (Ver. 1.0)  
Date Published December 2003 (K) Japan  
URL: http://www.elpida.com  
Elpida Memory,Inc. 2003  

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