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3D7502-25 PDF预览

3D7502-25

更新时间: 2024-02-02 01:06:43
品牌 Logo 应用领域
DATADELAY 解码器网络接口电信集成电路电信电路光电二极管
页数 文件大小 规格书
4页 35K
描述
MONOLITHIC MANCHESTER DECODER

3D7502-25 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.78Is Samacsys:N
JESD-30 代码:R-PDIP-T14长度:19.305 mm
功能数量:1端子数量:14
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:4.58 mm最大压摆率:40 mA
标称供电电压:5 V表面贴装:NO
技术:CMOS电信集成电路类型:MANCHESTER DECODER
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

3D7502-25 数据手册

 浏览型号3D7502-25的Datasheet PDF文件第2页浏览型号3D7502-25的Datasheet PDF文件第3页浏览型号3D7502-25的Datasheet PDF文件第4页 
3D7502  
Ò
MONOLITHIC MANCHESTER  
DECODER  
(SERIES 3D7502)  
data  
delay  
3
devices, inc.  
PACKAGES  
FEATURES  
RX  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VDD  
N/C  
·
·
·
All-silicon, low-power CMOS  
technology  
TTL/CMOS compatible inputs and  
outputs  
Vapor phase, IR and wave  
solderable  
Auto-insertable (DIP pkg.)  
Low ground bounce noise  
Maximum data rate: 50 MBaud  
Data rate range: ±15%  
N/C  
N/C  
N/C  
CLK  
N/C  
N/C  
RX  
CLK  
N/C  
1
2
3
4
8
7
6
5
VDD  
N/C  
N/C  
N/C  
N/C  
N/C  
·
·
·
·
GND  
8
DATB  
GND  
DATB  
3D7502M-xxx DIP (.300)  
3D7502H-xxx Gull Wing (.300)  
3D7502Z-xxx SOIC (.150)  
3D7502-xxx  
3D7502G-xxx Gull Wing (.300)  
3D7502D-xxx SOIC (.150)  
DIP (.300)  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The 3D7502 product family consists of monolithic CMOS Manchester  
Decoders. The unit accepts at the RX input a bi-phase-level,  
embedded-clock signal. In this encoding mode, a logic one is  
represented by a high-to-low transition within the bit cell, while a logic  
zero is represented by a low-to-high transition. The recovered clock  
and data signals are presented on CLK and DATB, respectively, with  
RX  
CLK  
Signal Input  
Signal Output (Clock)  
DATB Signal Output (Data)  
VCC +5 Volts  
GND Ground  
the data signal inverted. The operating baud rate (in MBaud) is specified by the dash number. The input  
baud rate may vary by as much as ±15% from the nominal device baud rate without compromising the  
integrity of the information received.  
Because the 3D7502 is not PLL-based, it does not require a long preamble in order to lock onto the  
received signal. Rather, the device requires at most one bit cell before the data presented at the output is  
valid. This is extremely useful in cases where the information arrives in bursts and the input is otherwise  
turned off.  
The all-CMOS 3D7502 integrated circuit has been designed as a reliable, economic alternative to hybrid  
TTL Manchester Decoders. It is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads. It is  
offered in standard 8-pin and 14-pin auto-insertable DIPs and space saving surface mount 8-pin and 14-  
pin SOICs.  
TABLE 1: PART NUMBER SPECIFICATIONS  
PART  
NUMBER  
3D7502-5  
3D7502-10  
3D7502-20  
3D7502-25  
3D7502-30  
3D7502-40  
3D7502-50  
BAUD RATE (MBaud)  
Nominal Minimum Maximum  
5.00  
10.00  
20.00  
25.00  
30.00  
40.00  
50.00  
4.25  
8.50  
5.75  
11.50  
23.00  
28.75  
34.50  
46.00  
57.50  
17.00  
21.25  
25.50  
34.00  
42.50  
NOTES: Any baud rate between 5 and 50 MBaud not shown is also available at no extra cost. Ó1997 Data Delay Devices  
Doc #97032  
5/19/97  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1

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