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CYV15G0401DXB-BGI PDF预览

CYV15G0401DXB-BGI

更新时间: 2024-01-05 11:04:49
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
53页 4144K
描述
Quad HOTLink II Transceiver

CYV15G0401DXB-BGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:HBGA, BGA256,20X20,50针数:256
Reach Compliance Code:compliantECCN代码:5A991.B.1
HTS代码:8542.39.00.01风险等级:5.62
Is Samacsys:N数据速率:1500000 Mbps
JESD-30 代码:S-PBGA-B256JESD-609代码:e1
长度:27 mm湿度敏感等级:3
功能数量:1端子数量:256
收发器数量:4最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:HBGA封装等效代码:BGA256,20X20,50
封装形状:SQUARE封装形式:GRID ARRAY, HEAT SINK/SLUG
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.745 mm
子类别:Network Interfaces最大压摆率:1.1 mA
标称供电电压:3.3 V表面贴装:YES
技术:BICMOS电信集成电路类型:ETHERNET TRANSCEIVER
温度等级:COMMERCIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:27 mmBase Number Matches:1

CYV15G0401DXB-BGI 数据手册

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CYP15G0401DXB  
CYV15G0401DXB  
Quad HOTLink II™ Transceiver  
• Dual differential PECL-compatible serial inputs per  
channel  
— Internal DC-restoration  
Features  
• Quad channel transceiver for 195 to 1500 MBaud serial  
signaling rate  
• Dual differential PECL-compatible serial outputs per  
— Aggregate throughput of 12 GBits/second  
• Second-generation HOTLink® technology  
• Compliant to multiple standards  
channel  
Source matched for 50transmission lines  
— No external bias resistors required  
— Signaling-rate controlled edge-rates  
• Compatible with  
— ESCON, DVB-ASI, Fibre Channel and Gigabit  
Ethernet (IEEE802.3z)  
— CYV15G0401DXB also compliant to SMPTE 259M  
and SMPTE 292M  
fiber-optic modules  
8B/10B encoded or 10-bit unencoded data  
• Selectable parity check/generate  
• Selectable multi-channel bonding options  
— Four 8-bit channels  
Two 16-bit channels  
— One 32-bit channel  
— copper cables  
— circuit board traces  
• JTAG boundary scan  
• Built-In Self-Test (BIST) for at-speed link testing  
• Per-channel Link Quality Indicator  
— Analog signal detect  
— N x 32-bit channel support (inter-chip)  
• Skew alignment support for multiple bytes of offset  
• Selectable input/output clocking options  
• MultiFrame™ Receive Framer  
— Digital signal detect  
• Low power 2.5W @ 3.3V typical  
• Single 3.3V supply  
• 256-ball thermally enhanced BGA  
0.25µ BiCMOS technology  
— Bit and Byte alignment  
Comma or full K28.5 detect  
Single- or multi-byte framer for byte alignment  
— Low-latency option  
Functional Description  
The CYP(V)15G0401DXB[1] Quad HOTLink II™ Transceiver  
is a point-to-point or point-to-multipoint communications  
building block allowing the transfer of data over high-speed  
serial links (optical fiber, balanced, and unbalanced copper  
transmission lines) at signaling speeds ranging from  
195-to-1500 MBaud per serial link.  
• Synchronous LVTTL parallel interface  
• Optional Elasticity Buffer in Receive Path  
• Optional Phase Align Buffer in Transmit Path  
• Internal phase-locked loops (PLLs) with no external  
PLL components  
10  
10  
10  
Serial Links  
10  
10  
10  
10  
10  
10  
10  
10  
Serial Links  
10  
10  
10  
10  
10  
Serial Links  
Serial Links  
Backplane or  
Cabled  
Connections  
Figure 1. HOTLink II System Connections  
Note:  
1. CYV15G0401DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYP15G0401DXB refers to devices not compliant to SMPTE 259M and SMPTE  
292M pathological test requirements. CYP(V)15G0401DXB refers to both devices.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-02002 Rev. *K  
Revised March 16, 2004  

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