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CYS25G0101DX-ATC

更新时间: 2024-02-08 05:05:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路信息通信管理异步传输模式
页数 文件大小 规格书
15页 214K
描述
SONET OC-48 Transceiver

CYS25G0101DX-ATC 技术参数

生命周期:Active包装说明:BGA, BGA100,10X10,40
Reach Compliance Code:compliant风险等级:5.82
JESD-30 代码:S-PBGA-B100端子数量:100
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA100,10X10,40封装形状:SQUARE
封装形式:GRID ARRAY电源:1.5,3.3 V
认证状态:Not Qualified子类别:ATM/SONET/SDH ICs
表面贴装:YES技术:BICMOS
电信集成电路类型:ATM/SONET/SDH TRANSCEIVER温度等级:COMMERCIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOMBase Number Matches:1

CYS25G0101DX-ATC 数据手册

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CYS25G0101DX  
SONET OC-48 Transceiver  
data recovery operations in a single chip, optimized for full  
SONET compliance.  
Features  
• SONET OC-48 operation  
• Bellcore and ITU jitter compliance  
• 2.488-GBaud serial signaling rate  
Transmit Path  
New data is accepted at the 16-bit parallel transmit interface  
at a rate of 155.52 MHz. This data is passed to a small  
integrated FIFO to allow flexible transfer of data between the  
SONET processor and the transmit serializer. As each 16-bit  
word is read from the transmit FIFO, it is serialized and sent  
out the high-speed differential line driver at a rate of 2.488  
Gbits/second.  
• Multiple selectable loopback/loop-through modes  
• Single 155.52-MHz reference clock  
• Transmit FIFO for flexible data interface clocking  
• 16-bit parallel-to-serial conversion in transmit path  
• Serial-to-16-bit parallel conversion in receive path  
• Synchronous parallel interface  
Receive Path  
— LVPECL-compliant  
As serial data is received at the differential line receiver, it is  
passed to a clock and data recovery (CDR) PLL, which  
extracts a precision low-jitter clock from the transitions in the  
data stream. This bit-rate clock is then used to sample the data  
stream and receive the data. Every 16-bit-times, a new word  
is presented at the receive parallel interface along with a clock.  
— HSTL-compliant  
• Internal transmit and receive phase-locked loops  
(PLLs)  
• Differential CML serial input  
— 50-mV input sensitivity  
Parallel Interface  
— 100Internal termination and DC-restoration  
• Differential CML serial output  
The parallel I/O interface supports high-speed bus communi-  
cations using HSTL signaling levels to minimize both power  
consumption and board landscape. The HSTL outputs are  
capable of driving unterminated transmission lines of less than  
70 mm, and terminated 50transmission lines of more than  
twice that length.  
Source matched for 50transmission lines (100Ω  
differential transmission lines)  
Direct interface to standard fiber-optic modules  
Less than 1.0W typical power  
The CYS25G0101DX Transceivers parallel HSTL I/O can  
also be configured to operate at LVPECL signaling levels. This  
can all be done externally by changing VDDQ, VREF, and  
creating a simple circuit at the termination of the transceivers  
parallel output interface.  
120-pin 14 mm × 14 mm TQFP  
Standby power-saving mode for inactive loops  
0.25µ BiCMOS technology  
Functional Description  
Clocking  
The CYS25G0101DX SONET OC-48 Transceiver is a  
communications building block for high-speed SONET data  
communications. It provides complete parallel-to-serial and  
serial-to-parallel conversion, clock generation, and clock and  
The source clock for the transmit data path is selectable from  
either the recovered clock or an external BITS (Building  
Integrated Timing Source) reference clock. The low jitter of the  
CYS25G0101DX  
TXD[15:0]  
16  
SONET Data  
Processor  
TXCLKI  
Transmit Data  
Interface  
FIFO_RST  
FIFO_ERR  
TXCLKO  
155.52 MHz  
BITS Time  
Reference  
2
REFCLK±  
16  
Host Bus  
Interface  
RXD[15:0]  
RXCLK  
Receive Data  
Interface  
IN+  
IN–  
SD  
OUT–  
OUT+  
RD+  
RD–  
SD  
TD–  
TD+  
Serial Data  
Serial Data  
LOOPTIME  
DIAGLOOP  
LOOPA  
Data & Clock  
Direction  
Control  
Optical  
XCVR  
Optical  
Fiber Links  
LINELOOP  
RESET  
PWRDN  
LOCKREF  
LFI  
Status and  
System  
Control  
Figure 1. CYS25G0101DX System Connections  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-02009 Rev. *J  
Revised December 30, 2002  

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