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CYP15G0402DX-BGI PDF预览

CYP15G0402DX-BGI

更新时间: 2024-02-14 05:10:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 电信集成电路电信电路信息通信管理
页数 文件大小 规格书
27页 818K
描述
Quad HOTLinkII SERDES

CYP15G0402DX-BGI 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256针数:256
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.92Is Samacsys:N
JESD-30 代码:S-PBGA-B256JESD-609代码:e0
长度:27 mm湿度敏感等级:3
功能数量:1端子数量:256
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA256,20X20,50封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):225
电源:1.5,3.3 V认证状态:Not Qualified
座面最大高度:1.745 mm子类别:Other Telecom ICs
标称供电电压:3.3 V表面贴装:YES
技术:BICMOS电信集成电路类型:TELECOM CIRCUIT
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:27 mmBase Number Matches:1

CYP15G0402DX-BGI 数据手册

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PRELIMINARY  
CYP15G0402DX  
Quad HOTLinkIISERDES  
Compatiblewith fiber-optic modules and copper cables  
JTAG boundary scan  
Built-in self-test (BIST) for at-speed link testing  
Per-channel Link Quality Indicator  
Analog signal detect  
Features  
• Second generation HOTLink® technology  
Fibre-Channel and Gigabit-Ethernet-compliant  
10-bit unencoded data transport  
Aggregate throughput of 12 GB/s  
Digital signal detect  
Low-power 3W typical  
256-ball BGA  
Selectable parity check/generate  
Four independently controlled 10-bit channels  
Selectable input clocking options  
0.25µ BiCMOS technology  
User selectable framing character  
Functional Description  
+Comma, ±comma, or full K28.5 detect  
Single or multicharacter framer for character align-  
The CYP15G0402DX Quad HOTLinkIISERDES is a  
point-to-point communications building block allowing the  
transfer of pre-encoded data over high-speed serial links  
(optical fiber, balanced, and unbalanced copper transmission  
lines) at speeds ranging from 200 to 1500 MBaud per serial  
link.  
ment  
Low-latency option  
Synchronous parallel input interface  
User-configurable threshold level  
Compatible with LVTTL, LVCMOS, LVTTL  
Synchronous parallel output interface  
Each transmit channel accepts pre-encoded 10-bit trans-  
mission characters in an input register, serializes each  
character, and drives it out a PECL-compatible differential line  
driver. Each receive channel accepts a serial data stream at a  
differential line receiver, deserializes the stream into 10-bit  
characters, frames these characters to the proper 10-bit  
character boundaries, and this data becomes register outputs  
with a recovered character clock. Figure 1 illustrates typical  
Compatible with LVTTL, LVCMOS, LVTTL  
200-to-1500 MBaud serial signaling rate  
Internal PLLs with no external PLL components  
Separate clock and data-recovery PLL per channel  
Common transmit clock multiplier PLL  
Differential PECL-compatible serial inputs  
Differential PECL-compatible serial outputs  
Source matched for 50transmission lines  
connections between independent systems and  
a
CYP15G0402DX.  
As  
a
second-generation  
HOTLink  
device,  
the  
CYP15G0402DX extends the HOTLink family to faster data  
rates, while maintaining serial link compatibility with other  
HOTLink devices.  
No external resistors required  
Adjustable amplitude for 100or 150balanced  
loads  
10  
Independent  
Serial Links  
Channel  
Transceiver  
10  
10  
10  
10  
10  
10  
10  
10  
10  
Independent  
Channel  
Transceiver  
10  
10  
Serial Links  
Serial Links  
Serial Links  
Independent  
Channel  
Transceiver  
10  
10  
Independent  
Channel  
Transceiver  
10  
10  
Cable or  
Optical  
Connections  
Figure 1. CYP15G0402DX HOTLink IISystem Connections  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-02023 Rev. *B  
Revised February 14, 2002  

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