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CYP15G0401DX-BGI PDF预览

CYP15G0401DX-BGI

更新时间: 2024-02-09 08:25:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
48页 1052K
描述
Telecom Circuit, 1-Func, BICMOS, PBGA256, 27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256

CYP15G0401DX-BGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, TBGA-256针数:256
Reach Compliance Code:unknown风险等级:5.07
Is Samacsys:NJESD-30 代码:S-PBGA-B256
JESD-609代码:e1长度:27 mm
湿度敏感等级:NOT SPECIFIED功能数量:1
端子数量:256最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):260
认证状态:COMMERCIAL座面最大高度:1.745 mm
标称供电电压:3.3 V表面贴装:YES
技术:BICMOS电信集成电路类型:TELECOM CIRCUIT
温度等级:COMMERCIAL端子面层:TIN SILVER COPPER
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:20
宽度:27 mmBase Number Matches:1

CYP15G0401DX-BGI 数据手册

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PRELIMINARY  
CYP15G0401DXA  
Quad HOTLink II™ Transceiver  
fiber-optic modules  
Features  
copper cables  
• 2nd generation HOTLink® technology  
• Fibre Channel and Gigabit Ethernet compliant 8B/10B-  
coded or 10-bit unencoded  
circuit board traces  
• JTAG boundary scan  
• 8-bit encoded data transport  
• 10-bit unencoded data transport  
• Selectable parity check/generate  
• Selectable multi-channel bonding options  
— Four 8-bit channels  
• Built-In Self-Test (BIST) for at-speed link testing  
• Per-channel Link Quality Indicator  
Analog signal detect  
Digital signal detect  
Frequency range detect  
• Low Power (2.8W typical)  
Single +3.3V VCC supply  
• 256-ball Thermally Enhanced BGA  
0.25µ BiCMOS technology  
— Two 16-bit channels  
— One 32-bit channel  
— N x 32-bit channel support (inter-chip)  
• Selectable input clocking options  
• Selectable output clocking options  
• MultiFrame™ receive framer provides alignment to  
— Bit, byte, half-word, word, multi-word  
Functional Description  
The CYP15G0401DXA Quad HOTLink IITransceiver is a  
point-to-point or point-to-multipoint communications building  
block allowing the transfer of data over high-speed serial links  
(optical fiber, balanced, and unbalanced copper transmission  
lines) at signaling speeds ranging from 200-to-1500 MBaud  
per serial link. The multiple channels in each device may be  
combined to allow transport of wide buses across significant  
distances with minimal concern for offsets in clock phase or  
link delay.  
— COMMA or Full K28.5 detect  
— Single or Multi-byte framer for byte alignment  
— Low-latency option  
• Skew alignment support for multiple bytes of offset  
• Synchronous LVTTL parallel input interface  
• Synchronous LVTTL parallel output interface  
• 200-to-1500 MBaud serial signaling rate  
• Internal PLLs with no external PLL components  
• Dual differential PECL-compatible serial inputs per  
channel  
• Dual differential PECL-compatible serial outputs per  
channel  
Each transmit channel accepts parallel characters in an Input  
Register, encodes each character for transport, and converts  
it to serial data. Each receive channel accepts serial data and  
converts it to parallel data, decodes the data into characters,  
and presents these characters to an output register. Figure 1  
illustrates typical connections between independent host sys-  
tems and corresponding CYP15G0401DXA parts. As a sec-  
ond-generation HOTLink device, the CYP15G0401DXA ex-  
tends the HOTLink family with enhanced levels of integration  
and faster data rates, while maintaining serial-link compatibility  
(data, command, and BIST) with other HOTLink devices.  
— Source matched for 50transmission lines  
— No external bias resistors required  
— Signaling-rate controlled edge-rates  
• Compatible with  
10  
10  
Serial Links  
10  
10  
10  
10  
10  
10  
10  
10  
10  
Serial Links  
10  
10  
10  
10  
10  
Serial Links  
Serial Links  
Backplane or  
Cabled  
Connections  
Figure 1. HOTLink IISystem Connections  
Cypress Semiconductor Corporation  
Document #: 38-02002 Rev. *B  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised July 10, 2001  

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