CY7C924ADX
200-MBaud HOTLinkâ Transceiver
The transmit section of the CY7C924ADX HOTLink can be
configured to accept either 8- or 10-bit data characters on
each clock cycle, and stores the parallel data into an internal
Transmit FIFO. Data is read from the Transmit FIFO and is
encoded using an embedded 8B/10B encoder to improve its
serial transmission characteristics. These encoded characters
are then serialized and output from two Positive ECL (PECL)
compatible differential transmission line drivers at a bit-rate of
10 or 12 times the character rate.
Features
• Second-generation HOTLink® technology
• Fibre Channel and ESCON®-compliant 8B/10B
encoder/decoder
• 10- or 12-bit pre-encoded data path (raw mode)
• 8- or 10-bit encoded data transport (using 8B/10B
coding)
• Synchronous or asynchronous TTL parallel interface
• UTOPIA compatible host bus interface
• Embedded/Bypassable 256-character synchronous
FIFOs
• Integrated support for daisy-chain and ring topologies
• Domain or individual destination device addressing
• 50- to 200-MBaud serial signaling rate
• Internal PLLs with no external PLL components
• Dual differential PECL-compatible serial inputs
• Dual differential PECL-compatible serial outputs
• Compatible with fiber-optic modules and copper cables
• Built-In Self-Test (BIST) for link testing
• Link Quality Indicator
The receive section of the CY7C924ADX HOTLink accepts a
serial bit-stream from one of two PECL-compatible differential
line receivers and, using a completely integrated PLL Clock
Synchronizer, recovers the timing information necessary for
data reconstruction. The recovered bit stream is deserialized
and framed into characters, 8B/10B decoded, and checked for
transmission errors. Recovered decoded characters are
reconstructed into either 8- or 10-bit data characters, written
to an internal Receive FIFO, and presented to the destination
host system.
The integrated 8B/10B encoder/decoder may be bypassed for
systems that present externally encoded or scrambled data at
the parallel interface. The embedded FIFOs may also be
bypassed to create a reference-locked serial transmission link.
For those systems requiring even greater FIFO storage
capability, external FIFOs may be directly coupled to the
CY7C924ADX device through the parallel interface without
additional glue-logic.
• Single +5.0V ±10% supply
• 100-pin TQFP
• 0.35m CMOS technology
Functional Description
The TTL parallel I/O interface may be configured as either a
FIFO (configurable for UTOPIA emulation or for depth
expansion through external FIFOs) or as a pipeline register
extender. The FIFO configurations are optimized for transport
of time-independent (asynchronous) 8- or 10-bit character-
oriented data across a link. A Built-In Self-Test (BIST) pattern
generator and checker permits at-speed testing of the high-
speed serial data paths in both the transmit and receive
sections, and across the interconnecting links.
The 200-MBaud CY7C924ADX HOTLink Transceiver is a
point-to-point communications building block allowing the
transfer of data over high-speed serial links (optical fiber,
balanced, and unbalanced copper transmission lines) at
speeds ranging between 50 and 200 MBaud. The transmit
section accepts parallel data of selectable width and converts
it to serial data, while the receiver section accepts serial data
and converts it to parallel data of selectable width. Figure1
illustrates typical connections between two independent host
systems and corresponding CY7C924ADX parts. As a second
generation HOTLink device, the CY7C924ADX provides
enhanced levels of technology, functionality, and integration
over the field-proven CY7B923/933 HOTLink.
HOTLink devices are ideal for a variety of applications where
parallel interfaces can be replaced with high-speed, point-to-
point serial links. Some applications include interconnecting
workstations, backplanes, servers, mass storage, and video
transmission equipment.
Transmit
Data
Data
Receive
Serial Link
Control
Control
Status
CY7C924ADX
CY7C924ADX
Status
Serial Link
Data
Transmit
Receive
Data
Figure 1.HOTLink System Connections
CypressSemiconductorCorporation
Document #: 38-02008 Rev. *D
•
3901NorthFirstStreet
•
SanJose, CA 95134
•
408-943-2600
Revised February 13, 2004
5秒后页面跳转
MAX487芯片引脚图及功能、应用领域详解
IR2110驱动芯片引脚图及功能、电路图详解
74LS74是什么芯片 74LS74引脚图及功能表
CD4511芯片引脚图及功能、电路图解析
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
