CY7C924ADX
200 MBaud HOTLink® Transceiver
The transmit section of the CY7C924ADX HOTLink can be
configured to accept either 8 or 10 bit data characters on each
clock cycle, and stores the parallel data in an internal Transmit
FIFO. Data is read from the Transmit FIFO and is encoded
using an embedded 8B/10B encoder to improve its serial
transmission characteristics. These encoded characters are
then serialized and output from two Positive ECL (PECL)
compatible differential transmission line drivers at a bit rate of
10 or 12 times the character rate.
Features
• Second generation HOTLink® technology
• Fibre Channel and ESCON® compliant 8B/10B
encoder/decoder
• 10 or 12 bit preencoded data path (raw mode)
• 8 or 10 bit encoded data transport (using 8B/10B coding)
• Synchronous or asynchronous TTL parallel interface
• UTOPIA compatible host bus interface
The receive section of the CY7C924ADX HOTLink accepts a
serial bit stream from one of two PECL compatible differential
• Embedded/Bypassable 256-character synchronous FIFOs
• Integrated support for daisy-chain and ring topologies
• Domain or individual destination device addressing
• 50 to 200 MBaud serial signaling rate
• Internal PLLs with no external PLL components
• Dual differential PECL compatible serial inputs
• Dual differential PECL compatible serial outputs
• Compatible with fiber optic modules and copper cables
• Built-In Self-Test (BIST) for link testing
• Link Quality Indicator
line receivers and, using a completely integrated PLL Clock
Synchronizer, recovers the timing information necessary for
data reconstruction. The recovered bit stream is deserialized
and framed into characters, 8B/10B decoded, and checked for
transmission errors. Recovered decoded characters are
reconstructed into either 8 or 10 bit data characters, written to
an internal Receive FIFO, and presented to the destination
host system.
Systems that present externally encoded or scrambled data at
the parallel interface may bypass the integrated 8B/10B
encoder/decoder. The embedded FIFOs may also be
bypassed to create a reference locked serial transmission link.
For those systems requiring even greater FIFO storage
capability, external FIFOs may directly couple to the
CY7C924ADX device through the parallel interface without
additional glue-logic.
• Single +5.0V ±10% supply
• 100-pin TQFP
• 0.35µ CMOS technology
• Pb-free package available
You can configure the TTL parallel I/O interface as either a
FIFO (configurable for UTOPIA emulation or for depth
expansion through external FIFOs) or as a pipeline register
extender. The FIFO configurations are optimized for transport
of time-independent (asynchronous) 8 or 10 bit character
oriented data across a link. A Built-In Self-Test (BIST) pattern
generator and checker permits at-speed testing of the high
speed serial data paths in both the transmit and receive
sections, and across the interconnecting links.
Functional Description
The 200 MBaud CY7C924ADX HOTLink Transceiver is a
point-to-point communications building block allowing the
transfer of data over high speed serial links (optical fiber,
balanced, and unbalanced copper transmission lines) at
speeds ranging between 50 and 200 MBaud. The transmit
section accepts parallel data of selectable width and converts
it to serial data, while the receiver section accepts serial data
and converts it to parallel data of selectable width. Figure 1
illustrates typical connections between two independent host
systems and corresponding CY7C924ADX parts. As a second
generation HOTLink device, the CY7C924ADX provides
enhanced levels of technology, functionality, and integration
over the field proven CY7B923/933 HOTLink.
HOTLink devices are ideal for a variety of applications where
parallel interfaces can be replaced with high speed,
point-to-point serial links. Some applications include intercon-
necting workstations, backplanes, servers, mass storage, and
video transmission equipment.
Figure 1. HOTLink System Connections
Transmit
Data
Data
Receive
Serial Link
Control
Control
Status
CY7C924ADX
CY7C924ADX
Status
Serial Link
Data
Transmit
Receive
Data
Cypress Semiconductor Corporation
Document #: 38-02008 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 27, 2007
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