1CY7C1041B
CY7C1041B
256K x 16 Static RAM
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Features
• High speed
— tAA = 12 ns
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O8 to I/O15. See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
• Low active power
— 1540 mW (max.)
• Low CMOS standby power (L version)
— 2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Functional Description
The CY7C1041B is a high-performance CMOS static RAM or-
ganized as 262,144 words by 16 bits.
The CY7C1041B is available in
a
standard 44-pin
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
SOJ
TSOP II
Top View
INPUT BUFFER
A
0
44
1
A
A
A
A
OE
BHE
BLE
I/O
I/O
I/O
0
17
16
15
A
43
42
41
40
39
38
1
A
2
3
4
5
6
1
A
2
A
2
I/O – I/O
256K x 16
ARRAY
0
7
A
3
4
A
3
A
A
4
1024 x 4096
A
I/O – I/O
5
6
8
15
CE
A
I/O
7
0
15
A
7
8
37
36
35
34
33
I/O
I/O
8
1
2
14
13
12
A
9
10
11
12
13
I/O
V
SS
I/O
3
CC
V
SS
COLUMN
DECODER
V
V
CC
I/O
32
31
30
29
28
27
I/O
I/O
4
5
6
7
11
10
I/O
I/O
I/O
14
15
16
I/O
I/O
NC
9
8
WE 17
18
BHE
A
A
14
A
13
A
12
A
11
5
WE
CE
OE
19
20
21
22
26
25
A
6
A
7
BLE
A
24
23
8
9
A
A
10
1041B–1
1041B–2
Selection Guide
7C1041B-12 7C1041B-15 7C1041B-17 7C1041B-20 7C1041B-25
Maximum Access Time (ns)
Maximum Operating Current (mA) Com’l
Ind’l
12
200
220
3
15
190
210
3
17
180
200
3
20
170
190
3
25
160
180
3
Maximum CMOS Standby Current Com’l
(mA)
Com’l
L
-
0.5
6
0.5
6
0.5
6
0.5
6
Ind’l
-
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
March 23, 2001
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