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CY7C09169A-9AI PDF预览

CY7C09169A-9AI

更新时间: 2024-01-26 14:54:20
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
17页 327K
描述
8K/16K x 9 Synchronous Dual-Port Static RAM

CY7C09169A-9AI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:PLASTIC, TQFP-100针数:100
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.88
Is Samacsys:N最长访问时间:20 ns
其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE最大时钟频率 (fCLK):67 MHz
I/O 类型:COMMONJESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
内存密度:147456 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:9湿度敏感等级:3
功能数量:1端口数量:2
端子数量:100字数:16384 words
字数代码:16000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:16KX9输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.0005 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.41 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

CY7C09169A-9AI 数据手册

 浏览型号CY7C09169A-9AI的Datasheet PDF文件第2页浏览型号CY7C09169A-9AI的Datasheet PDF文件第3页浏览型号CY7C09169A-9AI的Datasheet PDF文件第4页浏览型号CY7C09169A-9AI的Datasheet PDF文件第5页浏览型号CY7C09169A-9AI的Datasheet PDF文件第6页浏览型号CY7C09169A-9AI的Datasheet PDF文件第7页 
25/0251  
CY7C09159A  
CY7C09169A  
8K/16K x 9  
Synchronous Dual-Port Static RAM  
• High-speedclocktodataaccess6.5[1]/7.5/9/12ns(max.)  
• Low operating power  
Features  
• True dual-ported memory cells which allow simulta-  
neous access of the same memory location  
Active = 200 mA (typical)  
Standby = 0.05 mA (typical)  
• Two Flow-Through/Pipelined devices  
— 8K x 9 organization (CY7C09159A)  
— 16K x 9 organization (CY7C09169A)  
• Three Modes  
• Fully synchronous interface for easier operation  
• Burst counters increment addresses internally  
Shorten cycle times  
Minimize bus noise  
— Flow-Through  
Supported in Flow-Through and Pipelined modes  
• Dual Chip Enables for easy depth expansion  
• Automatic power-down  
• Commercial and Industrial temperature ranges  
Available in 100-pin TQFP  
— Pipelined  
— Burst  
• Pipelined output mode on both ports allows fast  
100-MHz cycle time  
• 0.35-micron CMOS for optimum speed/power  
v
Logic Block Diagram  
R/WL  
OEL  
R/WR  
OER  
CE0L  
CE0R  
1
1
CE1L  
CE1R  
0
0
0/1  
0/1  
1
0
0
1
0/1  
0/1  
FT/PipeL  
FT/PipeR  
9
9
I/O0LI/O8L  
I/O0RI/O8R  
I/O  
I/O  
Control  
Control  
13/14  
13/14  
[2]  
[2]  
A0A12/13L  
A0A12/13R  
Counter/  
Address  
Register  
Decode  
Counter/  
Address  
Register  
Decode  
CLKL  
CLKR  
ADSR  
True Dual-Ported  
RAM Array  
ADSL  
CNTENL  
CNTRSTL  
CNTENR  
CNTRSTR  
Notes:  
1. See page 6 for Load Conditions.  
2. A0A12 for 8K; A0A13 for 16K.  
For the most recent information, visit the Cypress web site at www.cypress.com  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-06047 Rev. *A  
Revised December 27, 2002  

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