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CY62127DV30L-55BVI PDF预览

CY62127DV30L-55BVI

更新时间: 2024-01-23 22:30:10
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
12页 375K
描述
1 Mb (64K x 16) Static RAM

CY62127DV30L-55BVI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:LEAD FREE, TSOP2-44
针数:44Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
Factory Lead Time:1 week风险等级:5.74
最长访问时间:55 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G44JESD-609代码:e4
长度:18.415 mm内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:44字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:64KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP44,.36,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:2.5/3.3 V
认证状态:Not Qualified座面最大高度:1.194 mm
最大待机电流:0.000004 A最小待机电流:1.5 V
子类别:SRAMs最大压摆率:0.01 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.2 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:10.16 mm
Base Number Matches:1

CY62127DV30L-55BVI 数据手册

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CY62127DV30  
MoBL®  
1 Mb (64K x 16) Static RAM  
also has an automatic power-down feature that significantly  
reduces power consumption by 90% when addresses are not  
toggling. The device can be put into standby mode reducing  
power consumption by more than 99% when deselected (CE  
HIGH or both BHE and BLE are HIGH). The input/output pins  
(I/O0 through I/O15) are placed in a high-impedance state  
when: deselected (CE HIGH), outputs are disabled (OE  
HIGH), both Byte High Enable and Byte Low Enable are  
disabled (BHE, BLE HIGH) or during a write operation (CE  
LOW and WE LOW).  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A15).  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
Features  
• Very high speed: 45 ns  
• Wide voltage range: 2.2V to 3.6V  
• Pin compatible with CY62127BV  
• Ultra-low active power  
— Typical active current: 0.85 mA @ f = 1 MHz  
— Typical active current: 5 mA @ f = fMAX  
• Ultra-low standby power  
• Easy memory expansion with CE and OE features  
• Automatic power-down when deselected  
• Packages offered in a 48-ball FBGA and a 44-lead TSOP  
Type II  
• Also available in Lead-Free 48-ball FBGA, and 44-lead  
TSOP Type II packages  
Functional Description[1]  
The CY62127DV30 is a high-performance CMOS static RAM  
organized as 64K words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
Logic Block Diagram  
DATA IN DRIVERS  
10  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
64K x 16  
RAM Array  
2048 x 512  
I/O0 – I/O7  
I/O8 – I/O15  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
CE  
Power -Down  
Circuit  
BHE  
BLE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-05229 Rev. *D  
Revised February 2, 2005  

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