Datasheet > CG6462AM

CG6462AM

更新时间： 2024-01-07 19:35:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		风扇控制器
页数	文件大小	规格书
25页	278K
描述
FAN Controller

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CG6462AM 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	8
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	边界扫描：	NO
总线兼容性：	I2C; USB	最大时钟频率：	24.6 MHz
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
长度：	4.889 mm	湿度敏感等级：	1
I/O 线路数量：	6	端子数量：	8
最高工作温度：	125 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
RAM（字数）：	256	座面最大高度：	1.727 mm
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	AUTOMOTIVE
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	3.8985 mm

CG6462AM 数据手册

PSoC™ Mixed-Signal Array

Preliminary Data Sheet

FAN Controller

CG6457AM and CG6462AM

Features

■ Excellent for Fan Control Applications

■ Flexible On-Chip Memory

■ Precision, Programmable Clocking

■ Internal ±3.5% 24 MHz Oscillator

■ 4K Flash Program Storage

■ 256 Bytes SRAM Data Storage

■ In-System Serial Programming (ISSP™)

■ Partial Flash Updates

■ Powerful Harvard Architecture Processor

■ M8C Processor Speeds to 12 MHz

■ Low Power at High Speed

■ Internal Oscillator for Watchdog and Sleep

■ Programmable Pin Configurations

■ 25 mA Drive on All GPIO

■ 4.75V to 5.25V Operating Voltage

■ Flexible Protection Modes

■ Extended Temperature Range:

■ Pull Up, Pull Down, High Z, Strong, or Open

-40°C to +125°C

Drain Drive Modes on All GPIO

■ Complete Development Tools

■ Advanced Peripherals (PSoC Blocks)

■ 4 Analog Type “E” PSoC Blocks Provide:

- 2 Comparators with DAC Refs

■ Up to 8 Analog Inputs on GPIO

■ Configurable Interrupt on All GPIO

■ Free Development Software

(PSoC™ Designer)

■ Full-Featured, In-Circuit Emulator and

Programmer

■ Additional System Resources

- Single or Dual 8-Bit 8:1 ADC

■ Full Speed Emulation

■ I²C™ Master, Slave and Multi-Master to

■ 4 Digital PSoC Blocks Provide:

- 8- to 32-Bit Timers, Counters, and PWMs

- CRC and PRS Modules

■ Complex Breakpoint Structure

■ 128 Bytes Trace Memory

400 kHz

■ Watchdog and Sleep Timers

- Full-Duplex UART, SPI™ Master or Slave

- Connectable to All GPIO Pins

■ User-Configurable Low Voltage Detection

■ Integrated Supervisory Circuit

■ Complex Peripherals by Combining Blocks

■ On-Chip Precision Voltage Reference

PSoC™ Functional Overview

Port 1 Port 0

PSoC

The PSoC™ family consists of many Mixed-Signal Array with

On-Chip Controller devices. These devices are designed to

replace multiple traditional MCU-based system components

with one, low cost single-chip programmable component. A

PSoC device includes configurable blocks of analog and digital

logic, as well as programmable interconnect. This architecture

allows the user to create customized peripheral configurations,

to match the requirements of each individual application. Addi-

tionally, a fast CPU, Flash program memory, SRAM data mem-

ory, and configurable IO are included in a range of convenient

pinouts.

CORE

SystemBus

Global Digital Interconnect

Global Analog Interconnect

Flash

CPUCore

SROM

SRAM

Sleep and

Watchdog

Interrupt

Controller

(M8C)

Clock Sources

The PSoC architecture, as illustrated on the left, is comprised of

four main areas: the Core, the System Resources, the Digital

System, and the Analog System. Configurable global bus

resources allow all the device resources to be combined into a

complete custom system. Each PSoC device includes four digi-

tal blocks. Depending on the PSoC package, up to two analog

comparators and up to 16 general purpose IO (GPIO) are also

included. The GPIO provide access to the global digital and

analog interconnects.

(Includes IMO and ILO)

DIGITAL SYSTEM

ANALOG SYSTEM

Analog

Ref.

Analog

PSoC Block

Array

Digital

PSoC Block

Array

The PSoC Core

The PSoC Core is a powerful engine that supports a rich

instruction set. It encompasses SRAM for data storage, an

interrupt controller, sleep and watchdog timers, and IMO (inter-

nal main oscillator) and ILO (internal low speed oscillator). The

POR and LVD

System Resets

Internal

Voltage

Ref.

Digital

I2C

Clocks

SYSTEM RESOURCES

May 24, 2005

12 3 4 5 6 7...25

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